traffic.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\temp\spartan2\veriloge\interface\traffic\traffic.ise -intstyle ise -e 3 -l 3
-s 6 -xml traffic traffic.ncd -o traffic.twr traffic.pcf


Design file:              traffic.ncd
Physical constraint file: traffic.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dataout<1>  |   13.753(R)|clk_BUFGP         |   0.000|
dataout<2>  |   13.539(R)|clk_BUFGP         |   0.000|
dataout<3>  |   14.350(R)|clk_BUFGP         |   0.000|
dataout<4>  |   13.848(R)|clk_BUFGP         |   0.000|
dataout<5>  |   13.228(R)|clk_BUFGP         |   0.000|
dataout<6>  |   13.388(R)|clk_BUFGP         |   0.000|
dataout<7>  |   14.092(R)|clk_BUFGP         |   0.000|
en<0>       |    9.031(R)|clk_BUFGP         |   0.000|
en<1>       |    9.314(R)|clk_BUFGP         |   0.000|
lightG<0>   |    9.628(R)|clk_BUFGP         |   0.000|
lightG<1>   |    9.830(R)|clk_BUFGP         |   0.000|
lightG<2>   |   10.224(R)|clk_BUFGP         |   0.000|
lightG<3>   |   10.398(R)|clk_BUFGP         |   0.000|
lightR<0>   |    9.158(R)|clk_BUFGP         |   0.000|
lightR<1>   |    8.906(R)|clk_BUFGP         |   0.000|
lightR<2>   |    9.153(R)|clk_BUFGP         |   0.000|
lightR<3>   |    9.246(R)|clk_BUFGP         |   0.000|
lightY<0>   |    9.240(R)|clk_BUFGP         |   0.000|
lightY<1>   |    9.894(R)|clk_BUFGP         |   0.000|
lightY<2>   |    9.331(R)|clk_BUFGP         |   0.000|
lightY<3>   |    9.859(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    9.528|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Mar 14 15:38:25 2006
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Peak Memory Usage: 62 MB