📄 clock.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: clock Date: 2-21-2006, 4:17PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
91 /144 ( 63%) 388 /720 ( 54%) 392/432 ( 91%) 74 /144 ( 51%) 18 /117 ( 15%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 7/18 54/54* 22/90 0/15
FB2 3/18 54/54* 7/90 0/15
FB3 14/18 54/54* 40/90 0/15
FB4 8/18 54/54* 65/90 6/15
FB5 18/18* 51/54 62/90 0/14
FB6 18/18* 29/54 55/90 9/13
FB7 18/18* 52/54 67/90 0/15
FB8 5/18 44/54 70/90 1/15
----- ----- ----- -----
91/144 392/432 388/720 16/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 18 109
Output : 16 16 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 18 18
** Power Data **
There are 91 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:895 - Unable to map all desired signals into function block, FB6,
because too many function block inputs are required. Buffering output signal
dataout<0> to allow all signals assigned to this function block to be placed.
************************* Summary of Mapped Logic ************************
** 16 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
dataout<1> 3 4 FB4_1 118 I/O O STD FAST
en<5> 4 20 FB4_2 126 I/O O STD FAST RESET
en<1> 4 20 FB4_3 133 I/O O STD FAST RESET
en<6> 4 20 FB4_9 131 I/O O STD FAST RESET
en<7> 4 20 FB4_11 132 I/O O STD FAST RESET
en<0> 4 20 FB4_12 134 I/O O STD FAST RESET
dataout<7> 4 4 FB6_2 106 I/O O STD FAST
dataout<5> 3 4 FB6_4 111 I/O O STD FAST
dataout<4> 4 4 FB6_8 113 I/O O STD FAST
dataout<2> 2 4 FB6_9 116 I/O O STD FAST
dataout<3> 2 4 FB6_10 115 I/O O STD FAST
dataout<0> 1 1 FB6_11 119 I/O O STD FAST
en<4> 4 20 FB6_12 120 I/O O STD FAST RESET
en<3> 4 20 FB6_15 124 I/O O STD FAST RESET
en<2> 4 20 FB6_17 125 I/O O STD FAST RESET
dataout<6> 4 4 FB8_16 107 I/O O STD FAST
** 75 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
cnt_scan<0> 2 3 FB1_12 STD RESET
cnt_scan<5> 3 8 FB1_13 STD RESET
cnt_scan<4> 3 7 FB1_14 STD RESET
cnt_scan<3> 3 6 FB1_15 STD RESET
cnt_scan<2> 3 5 FB1_16 STD RESET
cnt_scan<1> 3 4 FB1_17 STD RESET
dataout_buf_6_1 5 48 FB1_18 STD RESET
$OpTx$DEC_dataout_3_OBUF$4 2 3 FB2_16 STD
$OpTx$DEC_dataout_2_OBUF$3 2 4 FB2_17 STD
dataout_buf_7_0 3 49 FB2_18 STD RESET
$OpTx$DEC_dataout_3_OBUF$2 2 4 FB3_5 STD
$OpTx$DEC_dataout_2_OBUF$0 2 4 FB3_6 STD
dataout_buf_7_1 3 50 FB3_7 STD RESET
cnt<8> 3 11 FB3_8 STD RESET
cnt<7> 3 10 FB3_9 STD RESET
cnt<6> 3 9 FB3_10 STD RESET
cnt<5> 3 8 FB3_11 STD RESET
cnt<4> 3 7 FB3_12 STD RESET
cnt<3> 3 6 FB3_13 STD RESET
cnt<2> 3 5 FB3_14 STD RESET
cnt<1> 3 4 FB3_15 STD RESET
cnt<15> 3 18 FB3_16 STD RESET
cnt<13> 3 16 FB3_17 STD RESET
cnt<10> 3 13 FB3_18 STD RESET
dataout_code<0>/dataout_code<0>_D2 21 14 FB4_7 STD
dataout<0>_BUFR 21 32 FB4_16 STD
dataout_buf_7_2 3 51 FB5_1 STD RESET
dataout_buf_0_2 3 31 FB5_2 STD RESET
dataout_buf_0_0 3 29 FB5_3 STD RESET
cnt<24> 3 27 FB5_4 STD RESET
cnt<23> 3 26 FB5_5 STD RESET
cnt<20> 3 23 FB5_6 STD RESET
cnt<19> 3 22 FB5_7 STD RESET
cnt<18> 3 21 FB5_8 STD RESET
cnt<16> 3 19 FB5_9 STD RESET
cnt<0> 3 28 FB5_10 STD RESET
cnt<9> 4 28 FB5_11 STD RESET
cnt<25> 4 28 FB5_12 STD RESET
cnt<22> 4 28 FB5_13 STD RESET
cnt<21> 4 28 FB5_14 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
cnt<17> 4 28 FB5_15 STD RESET
cnt<14> 4 28 FB5_16 STD RESET
cnt<12> 4 28 FB5_17 STD RESET
cnt<11> 4 28 FB5_18 STD RESET
cnt_scan<9> 3 12 FB6_1 STD RESET
cnt_scan<8> 3 11 FB6_3 STD RESET
cnt_scan<7> 3 10 FB6_5 STD RESET
cnt_scan<6> 3 9 FB6_6 STD RESET
cnt_scan<15> 3 18 FB6_7 STD RESET
cnt_scan<14> 3 17 FB6_13 STD RESET
cnt_scan<13> 3 16 FB6_14 STD RESET
cnt_scan<12> 3 15 FB6_16 STD RESET
cnt_scan<10> 3 13 FB6_18 STD RESET
dataout_buf_7_3 3 52 FB7_1 STD RESET
dataout_buf_6_2 3 47 FB7_2 STD RESET
dataout_buf_6_0 3 45 FB7_3 STD RESET
dataout_buf_4_3 3 44 FB7_4 STD RESET
dataout_buf_4_0 3 41 FB7_5 STD RESET
dataout_buf_3_2 3 39 FB7_6 STD RESET
dataout_buf_3_0 3 37 FB7_7 STD RESET
dataout_buf_1_3 3 36 FB7_8 STD RESET
dataout_buf_1_0 3 33 FB7_9 STD RESET
dataout_buf_6_3 4 48 FB7_10 STD RESET
dataout_buf_4_2 4 44 FB7_11 STD RESET
dataout_buf_3_3 4 40 FB7_12 STD RESET
dataout_buf_1_2 4 36 FB7_13 STD RESET
dataout_buf_0_3 4 32 FB7_14 STD RESET
dataout_buf_4_1 5 44 FB7_15 STD RESET
dataout_buf_3_1 5 40 FB7_16 STD RESET
dataout_buf_1_1 5 36 FB7_17 STD RESET
dataout_buf_0_1 5 32 FB7_18 STD RESET
dataout_code<2>/dataout_code<2>_D2 21 14 FB8_1 STD
dataout_code<3>/dataout_code<3>_D2 21 14 FB8_6 STD
dataout_code<1>/dataout_code<1>_D2 21 14 FB8_13 STD
cnt_scan<11> 3 14 FB8_17 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
rst FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 54/0
Number of signals used by logic mapping into function block: 54
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
(unused) 0 0 0 5 FB1_3 17 I/O
(unused) 0 0 0 5 FB1_4 25 I/O
(unused) 0 0 0 5 FB1_5 19 I/O
(unused) 0 0 0 5 FB1_6 20 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 21 I/O
(unused) 0 0 0 5 FB1_9 22 I/O
(unused) 0 0 0 5 FB1_10 31 I/O
(unused) 0 0 0 5 FB1_11 24 I/O
cnt_scan<0> 2 0 0 3 FB1_12 26 I/O (b)
cnt_scan<5> 3 0 0 2 FB1_13 (b) (b)
cnt_scan<4> 3 0 0 2 FB1_14 27 I/O (b)
cnt_scan<3> 3 0 0 2 FB1_15 28 I/O (b)
cnt_scan<2> 3 0 0 2 FB1_16 35 I/O (b)
cnt_scan<1> 3 0 0 2 FB1_17 30 GCK/I/O (b)
dataout_buf_6_1 5 0 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 19: cnt<25> 37: dataout_buf_0_3
2: cnt<0> 20: cnt<2> 38: dataout_buf_1_0
3: cnt<10> 21: cnt<3> 39: dataout_buf_1_1
4: cnt<11> 22: cnt<4> 40: dataout_buf_1_2
5: cnt<12> 23: cnt<5> 41: dataout_buf_1_3
6: cnt<13> 24: cnt<6> 42: dataout_buf_3_0
7: cnt<14> 25: cnt<7> 43: dataout_buf_3_1
8: cnt<15> 26: cnt<8> 44: dataout_buf_3_2
9: cnt<16> 27: cnt<9> 45: dataout_buf_3_3
10: cnt<17> 28: cnt_scan<0> 46: dataout_buf_4_0
11: cnt<18> 29: cnt_scan<1> 47: dataout_buf_4_1
12: cnt<19> 30: cnt_scan<2> 48: dataout_buf_4_2
13: cnt<1> 31: cnt_scan<3> 49: dataout_buf_4_3
14: cnt<20> 32: cnt_scan<4> 50: dataout_buf_6_0
15: cnt<21> 33: cnt_scan<5> 51: dataout_buf_6_1
16: cnt<22> 34: dataout_buf_0_0 52: dataout_buf_6_2
17: cnt<23> 35: dataout_buf_0_1 53: dataout_buf_6_3
18: cnt<24> 36: dataout_buf_0_2 54: rst
Signal 1 2 3 4 5 6 FB
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