clock.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: clock.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "clock.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "clock"
Output Format                      : NGC
Target Device                      : xc2s50-6-TQ144

---- Source Options
Top Module Name                    : clock
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : clock.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "clock.v"
Module <clock> compiled
No errors in compilation
Analysis of file <"clock.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clock>.
WARNING:Xst:905 - "clock.v" line 41: The signals <dataout_buf> are missing in the sensitivity list of always block.
Module <clock> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <dataout_buf<2>> in unit <clock> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <dataout_buf<5>> in unit <clock> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <clock>.
    Related source file is "clock.v".
    Found 16x8-bit ROM for signal <dataout>.
    Found 8-bit register for signal <en>.
    Found 26-bit up counter for signal <cnt>.
    Found 16-bit up counter for signal <cnt_scan>.
    Found 4-bit up counter for signal <dataout_buf<7:6>>.
    Found 4-bit up counter for signal <dataout_buf<4:3>>.
    Found 4-bit up counter for signal <dataout_buf<1:0>>.
    Summary:
	inferred   1 ROM(s).
	inferred   8 Counter(s).
	inferred   8 D-type flip-flop(s).
Unit <clock> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Counters                         : 8
 16-bit up counter                 : 1
 26-bit up counter                 : 1
 4-bit up counter                  : 6
# Registers                        : 8
 1-bit register                    : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clock> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clock, actual ratio is 10.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : clock.ngr
Top Level Output File Name         : clock
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 18

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 40
#      1-bit register              : 40
# Adders/Subtractors               : 8
#      4-bit adder                 : 8

Cell Usage :
# BELS                             : 232
#      GND                         : 1
#      INV                         : 9
#      LUT1                        : 40
#      LUT2                        : 9
#      LUT2_D                      : 1
#      LUT3                        : 10
#      LUT3_D                      : 1
#      LUT4                        : 72
#      LUT4_D                      : 5
#      LUT4_L                      : 3
#      MUXCY                       : 40
#      VCC                         : 1
#      XORCY                       : 40
# FlipFlops/Latches                : 74
#      FDR                         : 42
#      FDRE                        : 23
#      FDRSE                       : 2
#      FDSE                        : 7
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 17
#      IBUF                        : 1
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      79  out of    768    10%  
 Number of Slice Flip Flops:            74  out of   1536     4%  
 Number of 4 input LUTs:               141  out of   1536     9%  
 Number of bonded IOBs:                 18  out of     96    18%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 74    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.431ns (Maximum Frequency: 87.481MHz)
   Minimum input arrival time before clock: 7.189ns
   Maximum output required time after clock: 23.474ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 11.431ns (frequency: 87.481MHz)
  Total number of paths / destination ports: 3175 / 152
-------------------------------------------------------------------------
Delay:               11.431ns (Levels of Logic = 4)
  Source:            cnt_22 (FF)
  Destination:       dataout_buf_4_2 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_22 to dataout_buf_4_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  cnt_22 (cnt_22)
     LUT4:I0->O            1   0.549   1.035  _n000371 (CHOICE764)
     LUT4:I1->O           11   0.549   2.070  _n0003120 (CHOICE779)
     LUT4:I0->O            6   0.549   1.665  _n0096 (_n0096)
     LUT3:I0->O            4   0.549   1.440  _n00081 (_n0008)
     FDRE:R                    0.734          dataout_buf_4_0
    ----------------------------------------
    Total                     11.431ns (4.015ns logic, 7.416ns route)
                                       (35.1% logic, 64.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 75 / 75
-------------------------------------------------------------------------
Offset:              7.189ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       dataout_buf_7_1 (FF)
  Destination Clock: clk rising

  Data Path: rst to dataout_buf_7_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.776   1.845  rst_IBUF (rst_IBUF)
     INV:I->O             29   0.549   3.285  dataout_buf_7__n00001_INV_0 (dataout_buf_7_0__n0000)
     FDRE:R                    0.734          dataout_buf_7_2
    ----------------------------------------
    Total                      7.189ns (2.059ns logic, 5.130ns route)
                                       (28.6% logic, 71.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 2664 / 16
-------------------------------------------------------------------------
Offset:              23.474ns (Levels of Logic = 10)
  Source:            en_4 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      clk rising

  Data Path: en_4 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDSE:C->Q             8   1.085   1.845  en_4 (en_4)
     LUT4:I0->O            4   0.549   1.440  _n006417 (CHOICE625)
     LUT4:I3->O            1   0.549   1.035  _n0064129 (CHOICE657)
     LUT2:I0->O            1   0.549   1.035  _n0064132 (CHOICE659)
     LUT4:I0->O            1   0.549   1.035  _n0064151_SW0 (N423)
     LUT4:I3->O            4   0.549   1.440  _n0064151 (_n0064)
     LUT4:I2->O            1   0.549   1.035  dataout_code<0>17 (CHOICE671)
     LUT4:I0->O            1   0.549   1.035  dataout_code<0>27_SW0 (N425)
     LUT4:I1->O            8   0.549   1.845  dataout_code<0>27 (dataout_code<0>)
     LUT4:I2->O            1   0.549   1.035  Mrom_dataout_inst_lut4_01 (dataout_0_OBUF)
     OBUF:I->O                 4.668          dataout_0_OBUF (dataout<0>)
    ----------------------------------------
    Total                     23.474ns (10.694ns logic, 12.780ns route)
                                       (45.6% logic, 54.4% route)

=========================================================================
CPU : 15.55 / 16.26 s | Elapsed : 16.00 / 16.00 s
 
--> 

Total memory usage is 76804 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    2 (   0 filtered)