clock.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\temp\spartan2\veriloge\interface\clock\clock.ise -intstyle ise -e 3 -l 3 -s
6 -xml clock clock.ncd -o clock.twr clock.pcf


Design file:              clock.ncd
Physical constraint file: clock.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
rst         |    6.806(R)|   -0.287(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dataout<0>  |   20.616(R)|clk_BUFGP         |   0.000|
dataout<1>  |   20.716(R)|clk_BUFGP         |   0.000|
dataout<2>  |   20.569(R)|clk_BUFGP         |   0.000|
dataout<3>  |   20.969(R)|clk_BUFGP         |   0.000|
dataout<4>  |   21.428(R)|clk_BUFGP         |   0.000|
dataout<5>  |   21.405(R)|clk_BUFGP         |   0.000|
dataout<6>  |   20.863(R)|clk_BUFGP         |   0.000|
dataout<7>  |   20.545(R)|clk_BUFGP         |   0.000|
en<0>       |    8.890(R)|clk_BUFGP         |   0.000|
en<1>       |    8.991(R)|clk_BUFGP         |   0.000|
en<2>       |    8.838(R)|clk_BUFGP         |   0.000|
en<3>       |    9.339(R)|clk_BUFGP         |   0.000|
en<4>       |    9.402(R)|clk_BUFGP         |   0.000|
en<5>       |    9.111(R)|clk_BUFGP         |   0.000|
en<6>       |    8.728(R)|clk_BUFGP         |   0.000|
en<7>       |    8.684(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    9.560|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Mar 14 15:12:31 2006
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Peak Memory Usage: 63 MB