mcu.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

--------------------------------------------------------------------------------
Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise e:\temp\spartan2\veriloge\interface\mcu\mcu.ise
-intstyle ise -e 3 -l 3 -s 6 -xml mcu mcu.ncd -o mcu.twr mcu.pcf


Design file:              mcu.ncd
Physical constraint file: mcu.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock mcu_ale
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
data<0>     |    0.893(F)|   -0.325(F)|mcu_ale_IBUF      |   0.000|
data<1>     |    0.609(F)|   -0.061(F)|mcu_ale_IBUF      |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock mcu_wr
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
data<0>     |   -0.059(F)|    1.523(F)|mcu_wr_IBUF       |   0.000|
data<1>     |   -0.059(F)|    1.523(F)|mcu_wr_IBUF       |   0.000|
data<2>     |   -0.059(F)|    1.523(F)|mcu_wr_IBUF       |   0.000|
data<3>     |    1.026(F)|   -0.363(F)|mcu_wr_IBUF       |   0.000|
data<4>     |    0.636(F)|    0.027(F)|mcu_wr_IBUF       |   0.000|
data<5>     |    2.028(F)|   -1.365(F)|mcu_wr_IBUF       |   0.000|
data<6>     |    0.871(F)|   -0.208(F)|mcu_wr_IBUF       |   0.000|
data<7>     |    0.327(F)|    0.336(F)|mcu_wr_IBUF       |   0.000|
------------+------------+------------+------------------+--------+

Clock mcu_ale to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
data<0>     |   12.359(F)|mcu_ale_IBUF      |   0.000|
data<1>     |   11.854(F)|mcu_ale_IBUF      |   0.000|
data<2>     |   11.893(F)|mcu_ale_IBUF      |   0.000|
data<3>     |   12.228(F)|mcu_ale_IBUF      |   0.000|
data<4>     |   11.765(F)|mcu_ale_IBUF      |   0.000|
data<5>     |   11.224(F)|mcu_ale_IBUF      |   0.000|
data<6>     |   11.230(F)|mcu_ale_IBUF      |   0.000|
data<7>     |   11.081(F)|mcu_ale_IBUF      |   0.000|
------------+------------+------------------+--------+

Clock mcu_wr to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
ledout<0>   |   12.676(F)|mcu_wr_IBUF       |   0.000|
ledout<1>   |   12.150(F)|mcu_wr_IBUF       |   0.000|
ledout<2>   |   12.057(F)|mcu_wr_IBUF       |   0.000|
ledout<3>   |   10.072(F)|mcu_wr_IBUF       |   0.000|
ledout<4>   |   10.016(F)|mcu_wr_IBUF       |   0.000|
ledout<5>   |    8.354(F)|mcu_wr_IBUF       |   0.000|
ledout<6>   |    9.871(F)|mcu_wr_IBUF       |   0.000|
ledout<7>   |    9.925(F)|mcu_wr_IBUF       |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock mcu_wr
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
mcu_ale        |         |         |         |    9.166|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
dial<0>        |data<0>        |    9.887|
dial<1>        |data<1>        |    9.114|
dial<2>        |data<2>        |    9.636|
dial<3>        |data<3>        |    9.586|
dial<4>        |data<4>        |    9.652|
dial<5>        |data<5>        |    8.808|
dial<6>        |data<6>        |    9.151|
dial<7>        |data<7>        |    9.110|
mcu_ale        |data<0>        |    7.839|
mcu_ale        |data<1>        |    7.596|
mcu_ale        |data<2>        |    7.740|
mcu_ale        |data<3>        |    7.830|
mcu_ale        |data<4>        |    7.936|
mcu_ale        |data<5>        |    8.449|
mcu_ale        |data<6>        |    8.449|
mcu_ale        |data<7>        |    7.983|
mcu_rd         |data<0>        |    7.756|
mcu_rd         |data<1>        |    7.513|
mcu_rd         |data<2>        |    7.657|
mcu_rd         |data<3>        |    7.747|
mcu_rd         |data<4>        |    7.853|
mcu_rd         |data<5>        |    8.366|
mcu_rd         |data<6>        |    8.366|
mcu_rd         |data<7>        |    7.900|
---------------+---------------+---------+

Analysis completed Sat Feb 25 18:51:04 2006
--------------------------------------------------------------------------------



Peak Memory Usage: 63 MB