dial.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\temp\spartan2\veriloge\interface\dial\dial.ise -intstyle ise -e 3 -l 3 -s 6
-xml dial dial.ncd -o dial.twr dial.pcf


Design file:              dial.ncd
Physical constraint file: dial.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
rst         |    3.474(R)|   -2.401(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dataout<2>  |   16.622(R)|clk_BUFGP         |   0.000|
dataout<3>  |   16.947(R)|clk_BUFGP         |   0.000|
dataout<4>  |   17.054(R)|clk_BUFGP         |   0.000|
dataout<7>  |   16.583(R)|clk_BUFGP         |   0.000|
en<0>       |    8.938(R)|clk_BUFGP         |   0.000|
en<1>       |    9.328(R)|clk_BUFGP         |   0.000|
en<2>       |    9.098(R)|clk_BUFGP         |   0.000|
en<3>       |    8.826(R)|clk_BUFGP         |   0.000|
en<4>       |    9.164(R)|clk_BUFGP         |   0.000|
en<5>       |    8.461(R)|clk_BUFGP         |   0.000|
en<6>       |    9.453(R)|clk_BUFGP         |   0.000|
en<7>       |    9.716(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.553|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
datain<0>      |dataout<2>     |   13.032|
datain<0>      |dataout<3>     |   13.357|
datain<0>      |dataout<4>     |   13.464|
datain<0>      |dataout<7>     |   12.993|
datain<1>      |dataout<2>     |   13.883|
datain<1>      |dataout<3>     |   14.208|
datain<1>      |dataout<4>     |   14.315|
datain<1>      |dataout<7>     |   13.844|
datain<2>      |dataout<2>     |   13.923|
datain<2>      |dataout<3>     |   14.248|
datain<2>      |dataout<4>     |   14.355|
datain<2>      |dataout<7>     |   13.884|
datain<3>      |dataout<2>     |   16.116|
datain<3>      |dataout<3>     |   16.441|
datain<3>      |dataout<4>     |   16.548|
datain<3>      |dataout<7>     |   16.077|
datain<4>      |dataout<2>     |   13.957|
datain<4>      |dataout<3>     |   14.282|
datain<4>      |dataout<4>     |   14.389|
datain<4>      |dataout<7>     |   13.918|
datain<5>      |dataout<2>     |   14.465|
datain<5>      |dataout<3>     |   14.790|
datain<5>      |dataout<4>     |   14.897|
datain<5>      |dataout<7>     |   14.426|
datain<6>      |dataout<2>     |   14.830|
datain<6>      |dataout<3>     |   15.155|
datain<6>      |dataout<4>     |   15.262|
datain<6>      |dataout<7>     |   14.791|
datain<7>      |dataout<2>     |   11.501|
datain<7>      |dataout<3>     |   11.826|
datain<7>      |dataout<4>     |   11.933|
datain<7>      |dataout<7>     |   11.462|
---------------+---------------+---------+

Analysis completed Tue Mar 14 15:13:40 2006
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Peak Memory Usage: 62 MB