ledwater.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\temp\spartan2\veriloge\interface\ledwater\ledwater.ise -intstyle ise -e 3 -l
3 -s 6 -xml ledwater ledwater.ncd -o ledwater.twr ledwater.pcf


Design file:              ledwater.ncd
Physical constraint file: ledwater.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dataout<0>  |    8.864(R)|clk_BUFGP         |   0.000|
dataout<10> |    8.644(R)|clk_BUFGP         |   0.000|
dataout<11> |    8.528(R)|clk_BUFGP         |   0.000|
dataout<1>  |    8.465(R)|clk_BUFGP         |   0.000|
dataout<2>  |    8.424(R)|clk_BUFGP         |   0.000|
dataout<3>  |    8.886(R)|clk_BUFGP         |   0.000|
dataout<4>  |    8.824(R)|clk_BUFGP         |   0.000|
dataout<5>  |    9.084(R)|clk_BUFGP         |   0.000|
dataout<6>  |    8.271(R)|clk_BUFGP         |   0.000|
dataout<7>  |    8.438(R)|clk_BUFGP         |   0.000|
dataout<8>  |    8.420(R)|clk_BUFGP         |   0.000|
dataout<9>  |    8.979(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.175|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Mar 14 15:27:30 2006
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Peak Memory Usage: 62 MB