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📄 i2c.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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	readData_reg<2> & readData_reg<3>
	# !en<0> & en<1> & writeData_reg<1> & 
	writeData_reg<2> & writeData_reg<3>
	# en<0> & !en<1> & !readData_reg<0> & 
	readData_reg<1> & !readData_reg<2> & !readData_reg<3>
	# !en<0> & en<1> & !writeData_reg<0> & 
	writeData_reg<1> & !writeData_reg<2> & !writeData_reg<3>;

MACROCELL | 7 | 15 | seg_data_6_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 7 | 16
INPUTS | 16 | en<0>  | readData_reg<0>  | readData_reg<1>  | readData_reg<3>  | readData_reg<4>  | readData_reg<5>  | readData_reg<6>  | readData_reg<7>  | rst  | phase1  | main_state_FFd1  | i2c_state_FFd1  | readData_reg<2>  | inner_state_FFd4  | inner_state_FFd2  | EXP41_.EXP
INPUTMC | 15 | 3 | 10 | 7 | 0 | 5 | 12 | 7 | 17 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 5 | 1 | 2 | 0 | 17 | 7 | 4 | 5 | 5 | 6 | 15 | 5 | 14 | 7 | 14
INPUTP | 1 | 79
EXPORTS | 1 | 7 | 16
IMPORTS | 1 | 7 | 14
EQ | 34 | 
   !seg_data<6> = en<0> & readData_reg<0> & !readData_reg<1> & 
	readData_reg<3> & !readData_reg<4> & !readData_reg<5> & 
	!readData_reg<6> & !readData_reg<7>
;Imported pterms FB8_15
	# !en<0> & writeData_reg<0> & !writeData_reg<1> & 
	writeData_reg<3>
	# en<0> & !readData_reg<0> & !readData_reg<2> & 
	!readData_reg<4> & !readData_reg<5> & !readData_reg<6> & 
	!readData_reg<7>
	# en<0> & !readData_reg<1> & !readData_reg<2> & 
	!readData_reg<4> & !readData_reg<5> & !readData_reg<6> & 
	!readData_reg<7>
	# en<0> & readData_reg<0> & readData_reg<1> & 
	!readData_reg<3> & !readData_reg<4> & !readData_reg<5> & 
	!readData_reg<6> & !readData_reg<7>
	# en<0> & !readData_reg<0> & !readData_reg<1> & 
	!readData_reg<3> & !readData_reg<4> & !readData_reg<5> & 
	!readData_reg<6> & !readData_reg<7>
;Imported pterms FB8_14
	# en<0> & en<1>
	# !en<0> & !writeData_reg<0> & !writeData_reg<2>
	# !en<0> & !writeData_reg<1> & !writeData_reg<2>
	# !en<0> & writeData_reg<0> & writeData_reg<1> & 
	!writeData_reg<3>
	# !en<0> & !writeData_reg<0> & !writeData_reg<1> & 
	!writeData_reg<3>
;Imported pterms FB8_13
	# !en<0> & !en<1>;
    seg_data_6_OBUF.EXP  =  rst & !phase1 & readData_reg<3>
	# rst & readData_reg<3> & !main_state_FFd1
	# rst & readData_reg<3> & !i2c_state_FFd1
	# rst & phase1 & readData_reg<2> & 
	inner_state_FFd4 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1

MACROCELL | 3 | 12 | seg_data<7>_BUFR.MC
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 5 | 1 | 3 | 13
INPUTS | 12 | en<0>  | en<1>  | readData_reg<4>  | readData_reg<5>  | readData_reg<6>  | readData_reg<0>  | readData_reg<1>  | readData_reg<2>  | writeData_reg<0>  | writeData_reg<1>  | writeData_reg<2>  | EXP14_.EXP
INPUTMC | 12 | 3 | 10 | 3 | 8 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 0 | 5 | 12 | 5 | 5 | 1 | 14 | 2 | 17 | 2 | 16 | 3 | 11
EXPORTS | 1 | 3 | 13
IMPORTS | 1 | 3 | 11
EQ | 26 | 
   seg_data<7>_BUFR = en<0> & !en<1> & readData_reg<4>
	# en<0> & !en<1> & readData_reg<5>
	# en<0> & !en<1> & readData_reg<6>
;Imported pterms FB4_12
	# en<0> & !en<1> & readData_reg<7>
	# !en<0> & en<1> & writeData_reg<0> & 
	writeData_reg<1> & !writeData_reg<2> & writeData_reg<3>
	# !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<1> & writeData_reg<2> & writeData_reg<3>
	# !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<1> & !writeData_reg<2> & !writeData_reg<3>
	# !en<0> & en<1> & !writeData_reg<0> & 
	!writeData_reg<1> & writeData_reg<2> & !writeData_reg<3>
;Imported pterms FB4_11
	# en<0> & !en<1> & readData_reg<0> & 
	readData_reg<1> & !readData_reg<2> & readData_reg<3>
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<1> & readData_reg<2> & readData_reg<3>
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<1> & !readData_reg<2> & !readData_reg<3>
	# en<0> & !en<1> & !readData_reg<0> & 
	!readData_reg<1> & readData_reg<2> & !readData_reg<3>;
    seg_data<7>_BUFR.EXP  =  en<0> & !en<1> & readData_reg<0> & 
	readData_reg<1> & readData_reg<2>
	# !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<1> & !writeData_reg<2>

MACROCELL | 6 | 12 | scl_OBUF
ATTRIBUTES | 8782626 | 0
OUTPUTMC | 2 | 6 | 11 | 6 | 13
INPUTS | 13 | rst  | phase0  | phase2  | main_state_FFd1  | i2c_state_FFd1  | phase3  | clk  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | i2c_state_FFd3  | main_state_FFd2  | EXP31_.EXP
INPUTMC | 11 | 1 | 3 | 1 | 1 | 0 | 17 | 7 | 4 | 1 | 0 | 6 | 15 | 5 | 15 | 5 | 0 | 7 | 8 | 0 | 16 | 6 | 11
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 6 | 13
IMPORTS | 1 | 6 | 11
EQ | 13 | 
   !scl.D = rst & !phase0 & phase2 & main_state_FFd1
;Imported pterms FB7_12
	# rst & !phase0 & phase2 & main_state_FFd2
	# rst & !phase0 & !scl & main_state_FFd1
	# rst & !phase0 & !scl & main_state_FFd2;
   scl.CLK = clk;
    scl_OBUF.EXP  =  rst & main_state_FFd1 & i2c_state_FFd1
	# rst & phase3 & inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 & 
	i2c_state_FFd3
	# rst & phase3 & inner_state_FFd4 & 
	inner_state_FFd1 & !inner_state_FFd3 & main_state_FFd2 & 
	i2c_state_FFd3

MACROCELL | 6 | 15 | inner_state_FFd4
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 46 | 6 | 4 | 7 | 0 | 5 | 12 | 5 | 5 | 7 | 17 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 5 | 6 | 15 | 5 | 15 | 0 | 17 | 5 | 0 | 5 | 14 | 0 | 16 | 7 | 7 | 6 | 12 | 7 | 4 | 6 | 1 | 2 | 2 | 2 | 5 | 6 | 10 | 5 | 6 | 2 | 9 | 2 | 13 | 2 | 8 | 0 | 0 | 5 | 1 | 5 | 4 | 5 | 11 | 5 | 13 | 5 | 16 | 5 | 17 | 6 | 0 | 6 | 3 | 6 | 8 | 6 | 9 | 6 | 14 | 6 | 17 | 7 | 2 | 7 | 3 | 7 | 6 | 7 | 9 | 7 | 11 | 7 | 15 | 7 | 16
INPUTS | 10 | rst  | phase3  | inner_state_FFd4  | main_state_FFd1  | main_state_FFd2  | inner_state_FFd1  | inner_state_FFd3  | EXP32_.EXP  | EXP33_.EXP  | clk
INPUTMC | 8 | 1 | 0 | 6 | 15 | 0 | 17 | 0 | 16 | 5 | 15 | 5 | 0 | 6 | 14 | 6 | 16
INPUTP | 2 | 79 | 143
IMPORTS | 2 | 6 | 14 | 6 | 16
EQ | 50 | 
   inner_state_FFd4.D = rst & !phase3 & inner_state_FFd4 & 
	main_state_FFd1
	# rst & !phase3 & inner_state_FFd4 & 
	main_state_FFd2
	# rst & inner_state_FFd1 & main_state_FFd1 & 
	inner_state_FFd3
	# rst & inner_state_FFd1 & inner_state_FFd3 & 
	main_state_FFd2
;Imported pterms FB7_15
	# rst & phase3 & inner_state_FFd1 & 
	main_state_FFd1 & !i2c_state_FFd3
	# rst & phase3 & inner_state_FFd1 & 
	main_state_FFd2 & i2c_state_FFd3
	# rst & inner_state_FFd4 & main_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2
	# rst & inner_state_FFd4 & !inner_state_FFd3 & 
	!inner_state_FFd2 & main_state_FFd2
	# rst & inner_state_FFd4 & main_state_FFd2 & 
	!i2c_state_FFd3 & i2c_state_FFd2
;Imported pterms FB7_14
	# rst & phase3 & main_state_FFd1 & 
	inner_state_FFd3 & inner_state_FFd2 & i2c_state_FFd1
	# rst & phase3 & inner_state_FFd3 & 
	inner_state_FFd2 & main_state_FFd2 & !i2c_state_FFd2
;Imported pterms FB7_17
	# rst & phase3 & inner_state_FFd1 & 
	main_state_FFd1 & i2c_state_FFd1
	# rst & phase3 & inner_state_FFd1 & 
	main_state_FFd2 & !i2c_state_FFd2
	# rst & phase3 & main_state_FFd1 & 
	inner_state_FFd3 & inner_state_FFd2 & !i2c_state_FFd3
	# rst & phase3 & main_state_FFd1 & 
	inner_state_FFd3 & inner_state_FFd2 & !i2c_state_FFd2
	# rst & phase3 & inner_state_FFd3 & 
	inner_state_FFd2 & main_state_FFd2 & i2c_state_FFd3
;Imported pterms FB7_18
	# rst & phase3 & !inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd1 & !i2c_state_FFd2
	# rst & inner_state_FFd4 & main_state_FFd1 & 
	i2c_state_FFd3 & i2c_state_FFd2 & !i2c_state_FFd1
	# rst & phase3 & main_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2 & !i2c_state_FFd3 & 
	!i2c_state_FFd2 & link
	# rst & phase3 & main_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2 & !i2c_state_FFd3 & 
	!i2c_state_FFd1 & link
	# rst & phase3 & !inner_state_FFd3 & 
	!inner_state_FFd2 & main_state_FFd2 & !i2c_state_FFd3 & 
	!i2c_state_FFd2 & link;
   inner_state_FFd4.CLK = clk;

MACROCELL | 5 | 15 | inner_state_FFd1
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 41 | 6 | 5 | 7 | 0 | 5 | 12 | 5 | 5 | 7 | 17 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 5 | 6 | 15 | 5 | 15 | 0 | 17 | 5 | 0 | 5 | 14 | 0 | 16 | 7 | 7 | 6 | 12 | 7 | 4 | 6 | 2 | 2 | 2 | 2 | 0 | 6 | 10 | 2 | 9 | 2 | 13 | 2 | 8 | 0 | 0 | 5 | 1 | 5 | 11 | 5 | 13 | 5 | 16 | 5 | 17 | 6 | 0 | 6 | 1 | 6 | 4 | 6 | 14 | 6 | 16 | 6 | 17 | 7 | 2 | 7 | 9 | 7 | 11 | 7 | 16
INPUTS | 14 | rst  | phase3  | inner_state_FFd4  | inner_state_FFd1  | main_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | i2c_state_FFd3  | main_state_FFd2  | i2c_state_FFd2  | i2c_state_FFd1  | clk  | inner_state_FFd2.EXP  | EXP21_.EXP
INPUTMC | 12 | 1 | 0 | 6 | 15 | 5 | 15 | 0 | 17 | 5 | 0 | 5 | 14 | 7 | 8 | 0 | 16 | 6 | 13 | 7 | 4 | 5 | 14 | 5 | 16
INPUTP | 2 | 79 | 143
IMPORTS | 2 | 5 | 14 | 5 | 16
EQ | 28 | 
   inner_state_FFd1.T = rst & phase3 & !inner_state_FFd4 & 
	!inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 & 
	inner_state_FFd2 & !i2c_state_FFd3
	# rst & phase3 & !inner_state_FFd4 & 
	!inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 & 
	inner_state_FFd2 & i2c_state_FFd1
	# rst & phase3 & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & inner_state_FFd2 & 
	main_state_FFd2 & i2c_state_FFd3
	# rst & phase3 & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & inner_state_FFd2 & 
	main_state_FFd2 & !i2c_state_FFd2
;Imported pterms FB6_15
	# rst & phase3 & !inner_state_FFd4 & 
	!inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 & 
	inner_state_FFd2 & !i2c_state_FFd2
;Imported pterms FB6_17
	# !rst & inner_state_FFd1
	# inner_state_FFd1 & !main_state_FFd1 & 
	!main_state_FFd2
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!main_state_FFd1 & !inner_state_FFd3 & !i2c_state_FFd2
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!inner_state_FFd3 & !i2c_state_FFd2 & !i2c_state_FFd1
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!inner_state_FFd3 & !main_state_FFd2 & !i2c_state_FFd3 & 
	!i2c_state_FFd1;
   inner_state_FFd1.CLK = clk;

MACROCELL | 0 | 17 | main_state_FFd1
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 54 | 6 | 7 | 7 | 0 | 5 | 12 | 5 | 5 | 7 | 16 | 7 | 12 | 7 | 10 | 6 | 17 | 7 | 5 | 0 | 15 | 1 | 14 | 2 | 17 | 2 | 16 | 2 | 15 | 6 | 12 | 6 | 15 | 5 | 15 | 0 | 17 | 5 | 0 | 5 | 14 | 0 | 0 | 7 | 7 | 6 | 13 | 7 | 4 | 6 | 2 | 2 | 1 | 2 | 7 | 2 | 14 | 5 | 1 | 5 | 4 | 5 | 10 | 5 | 11 | 5 | 13 | 5 | 16 | 5 | 17 | 6 | 3 | 6 | 4 | 6 | 5 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 14 | 6 | 16 | 7 | 1 | 7 | 2 | 7 | 3 | 7 | 6 | 7 | 8 | 7 | 9 | 7 | 11 | 7 | 15 | 7 | 17 | 0 | 16
INPUTS | 35 | rst  | main_state_FFd1  | phase3  | inner_state_FFd1  | inner_state_FFd3  | i2c_state_FFd2  | i2c_state_FFd1  | sda  | phase1  | inner_state_FFd4  | i2c_state_FFd3  | wr_input  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | main_state_FFd2  | cnt_delay<9>.EXP  | clk
INPUTMC | 32 | 0 | 17 | 1 | 0 | 5 | 15 | 5 | 0 | 6 | 13 | 7 | 4 | 6 | 7 | 1 | 2 | 6 | 15 | 7 | 8 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 16 | 0 | 0
INPUTP | 3 | 79 | 112 | 143
EXPORTS | 1 | 0 | 16
IMPORTS | 1 | 0 | 0
EQ | 24 | 
   main_state_FFd1.T = !rst & main_state_FFd1
	# phase3 & inner_state_FFd1 & main_state_FFd1 & 
	inner_state_FFd3 & i2c_state_FFd2 & i2c_state_FFd1
	# sda & phase1 & inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 & 
	!i2c_state_FFd3 & !i2c_state_FFd1
;Imported pterms FB1_1
	# sda & phase1 & inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 & 
	!i2c_state_FFd2 & !i2c_state_FFd1
	# !rd_input & rst & wr_input & !cnt_delay<0> & 
	cnt_delay<10> & cnt_delay<12> & cnt_delay<13> & cnt_delay<18> & 
	cnt_delay<8> & !cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & 
	!cnt_delay<16> & !cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> & 
	!cnt_delay<2> & !cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & 
	!cnt_delay<6> & !cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 & 
	!main_state_FFd2;
   main_state_FFd1.CLK = clk;
    main_state_FFd1.EXP  =  rst & !wr_input & !cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & 
	!cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & 
	!cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & 
	!cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & 
	!cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 & !main_state_FFd2

MACROCELL | 5 | 0 | inner_state_FFd3
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 48 | 6 | 7 | 7 | 0 | 5 | 12 | 5 | 5 | 7 | 17 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 5 | 6 | 15 | 5 | 15 | 0 | 1
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