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📄 i2c.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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MACROCELL | 7 | 5 | readData_reg<7>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 10 | 7 | 5 | 3 | 11 | 3 | 16 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 15 | 3 | 1 | 7 | 6 | 7 | 14
INPUTS | 13 | rst  | readData_reg<7>  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | phase1  | readData_reg<6>  | main_state_FFd1  | i2c_state_FFd1  | clk  | i2c_state_FFd1.EXP  | EXP37_.EXP
INPUTMC | 11 | 7 | 5 | 6 | 15 | 5 | 15 | 5 | 0 | 5 | 14 | 1 | 2 | 7 | 1 | 0 | 17 | 7 | 4 | 7 | 4 | 7 | 6
INPUTP | 2 | 79 | 143
IMPORTS | 2 | 7 | 4 | 7 | 6
EQ | 25 | 
   readData_reg<7>.D = rst & readData_reg<7> & inner_state_FFd4 & 
	inner_state_FFd1 & inner_state_FFd2
	# rst & readData_reg<7> & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2
	# rst & phase1 & readData_reg<6> & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<6> & 
	!inner_state_FFd1 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB8_5
	# rst & phase1 & readData_reg<6> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB8_7
	# rst & !phase1 & readData_reg<7>
	# rst & readData_reg<7> & !main_state_FFd1
	# rst & readData_reg<7> & !i2c_state_FFd1
	# rst & phase1 & readData_reg<6> & 
	inner_state_FFd4 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<6> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd3 & 
	i2c_state_FFd1;
   readData_reg<7>.CLK = clk;

MACROCELL | 0 | 15 | start_delaycnt
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 21 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15
INPUTS | 27 | rst  | start_delaycnt  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | main_state_FFd1  | main_state_FFd2  | wr_input  | rd_input  | clk
INPUTMC | 23 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17 | 0 | 16
INPUTP | 4 | 79 | 112 | 109 | 143
EQ | 23 | 
   start_delaycnt.T = !rst & start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt & !main_state_FFd1 & 
	!main_state_FFd2
	# !rd_input & rst & !cnt_delay<0> & !cnt_delay<10> & 
	!cnt_delay<12> & !cnt_delay<13> & !cnt_delay<18> & !cnt_delay<8> & 
	!cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & 
	!cnt_delay<17> & !cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & 
	!cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & 
	!cnt_delay<7> & !cnt_delay<9> & !start_delaycnt & !main_state_FFd1 & 
	!main_state_FFd2
	# rst & !wr_input & !cnt_delay<0> & !cnt_delay<10> & 
	!cnt_delay<12> & !cnt_delay<13> & !cnt_delay<18> & !cnt_delay<8> & 
	!cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & 
	!cnt_delay<17> & !cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & 
	!cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & 
	!cnt_delay<7> & !cnt_delay<9> & !start_delaycnt & !main_state_FFd1 & 
	!main_state_FFd2;
   start_delaycnt.CLK = clk;

MACROCELL | 1 | 14 | writeData_reg<0>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 16 | 1 | 14 | 3 | 0 | 3 | 16 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 14 | 3 | 11 | 5 | 6 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 17 | 5 | 2 | 5 | 8 | 7 | 13
INPUTS | 6 | rst  | writeData_reg<0>  | main_state_FFd1  | main_state_FFd2  | data_in<0>  | clk
INPUTMC | 3 | 1 | 14 | 0 | 17 | 0 | 16
INPUTP | 3 | 79 | 77 | 143
EQ | 5 | 
   !writeData_reg<0>.D = rst & !writeData_reg<0> & main_state_FFd1
	# rst & !writeData_reg<0> & main_state_FFd2
	# rst & !main_state_FFd1 & !main_state_FFd2 & 
	!data_in<0>;
   writeData_reg<0>.CLK = clk;

MACROCELL | 2 | 17 | writeData_reg<1>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 15 | 2 | 17 | 3 | 0 | 3 | 16 | 5 | 8 | 3 | 13 | 5 | 2 | 7 | 14 | 3 | 11 | 5 | 6 | 3 | 1 | 3 | 12 | 3 | 14 | 3 | 15 | 3 | 17 | 7 | 13
INPUTS | 6 | rst  | writeData_reg<1>  | main_state_FFd1  | main_state_FFd2  | data_in<1>  | clk
INPUTMC | 3 | 2 | 17 | 0 | 17 | 0 | 16
INPUTP | 3 | 79 | 74 | 143
EQ | 5 | 
   writeData_reg<1>.D = rst & writeData_reg<1> & main_state_FFd1
	# rst & writeData_reg<1> & main_state_FFd2
	# rst & !main_state_FFd1 & !main_state_FFd2 & 
	data_in<1>;
   writeData_reg<1>.CLK = clk;

MACROCELL | 2 | 16 | writeData_reg<2>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 14 | 2 | 16 | 3 | 0 | 3 | 15 | 5 | 8 | 3 | 13 | 5 | 3 | 7 | 13 | 3 | 11 | 5 | 6 | 3 | 1 | 3 | 12 | 3 | 14 | 3 | 17 | 5 | 2
INPUTS | 6 | rst  | writeData_reg<2>  | main_state_FFd1  | main_state_FFd2  | data_in<2>  | clk
INPUTMC | 3 | 2 | 16 | 0 | 17 | 0 | 16
INPUTP | 3 | 79 | 72 | 143
EQ | 5 | 
   !writeData_reg<2>.D = rst & !writeData_reg<2> & main_state_FFd1
	# rst & !writeData_reg<2> & main_state_FFd2
	# rst & !main_state_FFd1 & !main_state_FFd2 & 
	!data_in<2>;
   writeData_reg<2>.CLK = clk;

MACROCELL | 2 | 15 | writeData_reg<3>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 15 | 2 | 15 | 3 | 0 | 3 | 16 | 5 | 9 | 3 | 1 | 5 | 3 | 7 | 14 | 3 | 11 | 2 | 6 | 3 | 14 | 3 | 15 | 3 | 17 | 5 | 2 | 5 | 8 | 7 | 13
INPUTS | 6 | rst  | writeData_reg<3>  | main_state_FFd1  | main_state_FFd2  | data_in<3>  | clk
INPUTMC | 3 | 2 | 15 | 0 | 17 | 0 | 16
INPUTP | 3 | 79 | 69 | 143
EQ | 5 | 
   writeData_reg<3>.D = rst & writeData_reg<3> & main_state_FFd1
	# rst & writeData_reg<3> & main_state_FFd2
	# rst & !main_state_FFd1 & !main_state_FFd2 & 
	data_in<3>;
   writeData_reg<3>.CLK = clk;

MACROCELL | 3 | 0 | seg_data_1_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 10 | en<1>  | readData_reg<0>  | readData_reg<1>  | readData_reg<2>  | readData_reg<3>  | writeData_reg<0>  | writeData_reg<1>  | writeData_reg<2>  | writeData_reg<3>  | EXP13_.EXP
INPUTMC | 10 | 3 | 8 | 7 | 0 | 5 | 12 | 5 | 5 | 7 | 17 | 1 | 14 | 2 | 17 | 2 | 16 | 2 | 15 | 3 | 1
IMPORTS | 1 | 3 | 1
EQ | 20 | 
   seg_data<1> = !en<1> & !readData_reg<1> & !readData_reg<2> & 
	!readData_reg<3>
	# en<1> & writeData_reg<0> & writeData_reg<1> & 
	writeData_reg<2> & !writeData_reg<3>
	# en<1> & !writeData_reg<0> & !writeData_reg<1> & 
	writeData_reg<2> & writeData_reg<3>
	# !en<1> & readData_reg<0> & readData_reg<1> & 
	readData_reg<2> & !readData_reg<3>
	# !en<1> & !readData_reg<0> & !readData_reg<1> & 
	readData_reg<2> & readData_reg<3>
;Imported pterms FB4_2
	# !en<1> & readData_reg<4>
	# !en<1> & readData_reg<5>
	# !en<1> & readData_reg<6>
	# !en<1> & readData_reg<7>
	# en<1> & !writeData_reg<1> & !writeData_reg<2> & 
	!writeData_reg<3>
;Imported pterms FB4_3
	# en<0> & en<1>
	# !en<0> & !en<1>;

MACROCELL | 3 | 16 | seg_data<2>_BUFR.MC
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 5 | 7
INPUTS | 11 | en<0>  | en<1>  | readData_reg<4>  | readData_reg<5>  | readData_reg<6>  | readData_reg<7>  | writeData_reg<0>  | writeData_reg<1>  | writeData_reg<3>  | EXP16_.EXP  | cnt_scan<9>.EXP
INPUTMC | 11 | 3 | 10 | 3 | 8 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 5 | 1 | 14 | 2 | 17 | 2 | 15 | 3 | 15 | 3 | 17
IMPORTS | 2 | 3 | 15 | 3 | 17
EQ | 22 | 
   seg_data<2>_BUFR = en<0> & !en<1> & readData_reg<4>
	# en<0> & !en<1> & readData_reg<5>
	# en<0> & !en<1> & readData_reg<6>
	# en<0> & !en<1> & readData_reg<7>
	# !en<0> & en<1> & writeData_reg<0> & 
	writeData_reg<1> & !writeData_reg<3>
;Imported pterms FB4_16
	# en<0> & !en<1> & readData_reg<0> & 
	readData_reg<1> & !readData_reg<3>
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<2> & !readData_reg<3>
	# en<0> & !en<1> & readData_reg<1> & 
	!readData_reg<2> & !readData_reg<3>
	# !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<2> & !writeData_reg<3>
	# !en<0> & en<1> & writeData_reg<1> & 
	!writeData_reg<2> & !writeData_reg<3>
;Imported pterms FB4_18
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<1> & readData_reg<2> & readData_reg<3>
	# !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<1> & writeData_reg<2> & writeData_reg<3>;

MACROCELL | 5 | 9 | seg_data_3_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 9 | en<0>  | en<1>  | readData_reg<4>  | readData_reg<5>  | readData_reg<6>  | readData_reg<7>  | writeData_reg<0>  | writeData_reg<3>  | _12_.EXP
INPUTMC | 9 | 3 | 10 | 3 | 8 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 5 | 1 | 14 | 2 | 15 | 5 | 8
IMPORTS | 1 | 5 | 8
EQ | 17 | 
   seg_data<3> = en<0> & !en<1> & readData_reg<4>
	# en<0> & !en<1> & readData_reg<5>
	# en<0> & !en<1> & readData_reg<6>
	# en<0> & !en<1> & readData_reg<7>
	# !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<3>
;Imported pterms FB6_9
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<3>
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<1> & !readData_reg<2>
	# en<0> & !en<1> & !readData_reg<1> & 
	readData_reg<2> & !readData_reg<3>
	# !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<1> & !writeData_reg<2>
	# !en<0> & en<1> & !writeData_reg<1> & 
	writeData_reg<2> & !writeData_reg<3>;

MACROCELL | 3 | 13 | seg_data<4>_BUFR.MC
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 5 | 7
INPUTS | 11 | en<0>  | en<1>  | readData_reg<4>  | readData_reg<5>  | readData_reg<6>  | readData_reg<7>  | writeData_reg<0>  | writeData_reg<1>  | writeData_reg<2>  | seg_data<7>_BUFR.EXP  | EXP15_.EXP
INPUTMC | 11 | 3 | 10 | 3 | 8 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 5 | 1 | 14 | 2 | 17 | 2 | 16 | 3 | 12 | 3 | 14
IMPORTS | 2 | 3 | 12 | 3 | 14
EQ | 22 | 
   seg_data<4>_BUFR = en<0> & !en<1> & readData_reg<4>
	# en<0> & !en<1> & readData_reg<5>
	# en<0> & !en<1> & readData_reg<6>
	# en<0> & !en<1> & readData_reg<7>
	# !en<0> & en<1> & writeData_reg<0> & 
	writeData_reg<1> & writeData_reg<2>
;Imported pterms FB4_13
	# en<0> & !en<1> & readData_reg<0> & 
	readData_reg<1> & readData_reg<2>
	# !en<0> & en<1> & writeData_reg<0> & 
	!writeData_reg<1> & !writeData_reg<2>
;Imported pterms FB4_15
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<1> & !readData_reg<2>
	# en<0> & !en<1> & !readData_reg<0> & 
	readData_reg<1> & !readData_reg<2> & readData_reg<3>
	# en<0> & !en<1> & !readData_reg<0> & 
	!readData_reg<1> & readData_reg<2> & !readData_reg<3>
	# !en<0> & en<1> & !writeData_reg<0> & 
	writeData_reg<1> & !writeData_reg<2> & writeData_reg<3>
	# !en<0> & en<1> & !writeData_reg<0> & 
	!writeData_reg<1> & writeData_reg<2> & !writeData_reg<3>;

MACROCELL | 5 | 3 | seg_data_5_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 10 | en<0>  | en<1>  | readData_reg<4>  | readData_reg<5>  | readData_reg<6>  | readData_reg<7>  | writeData_reg<0>  | writeData_reg<2>  | writeData_reg<3>  | EXP17_.EXP
INPUTMC | 10 | 3 | 10 | 3 | 8 | 7 | 12 | 7 | 10 | 7 | 1 | 7 | 5 | 1 | 14 | 2 | 16 | 2 | 15 | 5 | 2
IMPORTS | 1 | 5 | 2
EQ | 17 | 
   seg_data<5> = en<0> & !en<1> & readData_reg<4>
	# en<0> & !en<1> & readData_reg<5>
	# en<0> & !en<1> & readData_reg<6>
	# en<0> & !en<1> & readData_reg<7>
	# !en<0> & en<1> & !writeData_reg<0> & 
	writeData_reg<2> & writeData_reg<3>
;Imported pterms FB6_3
	# en<0> & !en<1> & !readData_reg<0> & 
	readData_reg<2> & readData_reg<3>
	# en<0> & !en<1> & readData_reg<1> &
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