i2c.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

	# rst & sda.PIN & phase1 & !inner_state_FFd4 & 
	main_state_FFd1 & inner_state_FFd3 & i2c_state_FFd1
	# rst & sda.PIN & phase1 & !inner_state_FFd4 & 
	main_state_FFd1 & inner_state_FFd2 & i2c_state_FFd1;
   readData_reg<0>.CLK = clk;

MACROCELL | 5 | 12 | readData_reg<1>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 16 | 5 | 12 | 5 | 5 | 3 | 0 | 3 | 15 | 5 | 8 | 3 | 12 | 5 | 2 | 7 | 15 | 3 | 10 | 3 | 14 | 3 | 17 | 5 | 4 | 5 | 10 | 5 | 11 | 7 | 14 | 5 | 13
INPUTS | 16 | rst  | readData_reg<1>  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | phase1  | readData_reg<0>  | main_state_FFd1  | i2c_state_FFd1  | clk  | main_state_FFd2  | i2c_state_FFd3  | i2c_state_FFd2  | phase3  | EXP19_.EXP
INPUTMC | 14 | 5 | 12 | 6 | 15 | 5 | 15 | 5 | 0 | 5 | 14 | 1 | 2 | 7 | 0 | 0 | 17 | 7 | 4 | 0 | 16 | 7 | 8 | 6 | 13 | 1 | 0 | 5 | 11
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 5 | 13
IMPORTS | 1 | 5 | 11
EQ | 30 | 
   readData_reg<1>.D = rst & readData_reg<1> & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2
	# rst & phase1 & readData_reg<0> & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB6_12
	# rst & readData_reg<1> & inner_state_FFd4 & 
	inner_state_FFd1 & inner_state_FFd2
	# rst & phase1 & readData_reg<0> & 
	inner_state_FFd4 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<0> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd3 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<0> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<0> & 
	!inner_state_FFd1 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB6_11
	# rst & !phase1 & readData_reg<1>
	# rst & readData_reg<1> & !main_state_FFd1
	# rst & readData_reg<1> & !i2c_state_FFd1;
   readData_reg<1>.CLK = clk;
    readData_reg<1>.EXP  =  !inner_state_FFd1 & !inner_state_FFd2 & 
	!main_state_FFd2 & i2c_state_FFd3 & i2c_state_FFd2 & !i2c_state_FFd1
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!inner_state_FFd3 & !main_state_FFd2 & !i2c_state_FFd3 & 
	!i2c_state_FFd1

MACROCELL | 5 | 5 | readData_reg<2>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 14 | 5 | 5 | 7 | 16 | 3 | 0 | 3 | 15 | 5 | 8 | 3 | 12 | 5 | 2 | 7 | 14 | 3 | 10 | 3 | 14 | 3 | 17 | 5 | 4 | 5 | 6 | 7 | 15
INPUTS | 13 | rst  | readData_reg<2>  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | phase1  | readData_reg<1>  | main_state_FFd1  | i2c_state_FFd1  | clk  | EXP18_.EXP  | $OpTx$FX_DC$70.EXP
INPUTMC | 11 | 5 | 5 | 6 | 15 | 5 | 15 | 5 | 0 | 5 | 14 | 1 | 2 | 5 | 12 | 0 | 17 | 7 | 4 | 5 | 4 | 5 | 6
INPUTP | 2 | 79 | 143
IMPORTS | 2 | 5 | 4 | 5 | 6
EQ | 25 | 
   readData_reg<2>.D = rst & readData_reg<2> & inner_state_FFd4 & 
	inner_state_FFd1 & inner_state_FFd2
	# rst & readData_reg<2> & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2
	# rst & phase1 & readData_reg<1> & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<1> & 
	!inner_state_FFd1 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB6_5
	# rst & !phase1 & readData_reg<2>
	# rst & readData_reg<2> & !main_state_FFd1
	# rst & phase1 & readData_reg<1> & 
	inner_state_FFd4 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<1> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd3 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<1> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB6_7
	# rst & readData_reg<2> & !i2c_state_FFd1;
   readData_reg<2>.CLK = clk;

MACROCELL | 7 | 17 | readData_reg<3>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 14 | 7 | 17 | 7 | 12 | 3 | 0 | 3 | 15 | 5 | 8 | 3 | 10 | 5 | 2 | 7 | 15 | 3 | 14 | 3 | 17 | 7 | 11 | 7 | 14 | 7 | 16 | 7 | 0
INPUTS | 12 | rst  | readData_reg<3>  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | sda.PIN  | phase1  | main_state_FFd1  | i2c_state_FFd1  | clk  | EXP42_.EXP
INPUTMC | 9 | 7 | 17 | 6 | 15 | 5 | 15 | 5 | 0 | 5 | 14 | 1 | 2 | 0 | 17 | 7 | 4 | 7 | 16
INPUTP | 3 | 79 | 88 | 143
EXPORTS | 1 | 7 | 0
IMPORTS | 1 | 7 | 16
EQ | 31 | 
   readData_reg<3>.D = rst & readData_reg<3> & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2
;Imported pterms FB8_17
	# rst & readData_reg<3> & inner_state_FFd4 & 
	inner_state_FFd1 & inner_state_FFd2
	# rst & phase1 & readData_reg<2> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd3 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<2> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<2> & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<2> & 
	!inner_state_FFd1 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB8_16
	# rst & !phase1 & readData_reg<3>
	# rst & readData_reg<3> & !main_state_FFd1
	# rst & readData_reg<3> & !i2c_state_FFd1
	# rst & phase1 & readData_reg<2> & 
	inner_state_FFd4 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1;
   readData_reg<3>.CLK = clk;
    readData_reg<3>.EXP  =  rst & sda.PIN & phase1 & inner_state_FFd4 & 
	main_state_FFd1 & !inner_state_FFd2 & i2c_state_FFd1
	# rst & sda.PIN & phase1 & !inner_state_FFd4 & 
	main_state_FFd1 & inner_state_FFd3 & i2c_state_FFd1
	# rst & sda.PIN & phase1 & !inner_state_FFd4 & 
	main_state_FFd1 & inner_state_FFd2 & i2c_state_FFd1

MACROCELL | 7 | 12 | readData_reg<4>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 13 | 7 | 12 | 7 | 10 | 3 | 12 | 3 | 16 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 15 | 3 | 1 | 7 | 9 | 7 | 11 | 7 | 14 | 7 | 13
INPUTS | 14 | rst  | readData_reg<4>  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | phase1  | readData_reg<3>  | main_state_FFd1  | i2c_state_FFd1  | clk  | en<0>  | en<1>  | EXP39_.EXP
INPUTMC | 12 | 7 | 12 | 6 | 15 | 5 | 15 | 5 | 0 | 5 | 14 | 1 | 2 | 7 | 17 | 0 | 17 | 7 | 4 | 3 | 10 | 3 | 8 | 7 | 11
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 7 | 13
IMPORTS | 1 | 7 | 11
EQ | 26 | 
   readData_reg<4>.D = rst & readData_reg<4> & inner_state_FFd4 & 
	inner_state_FFd1 & inner_state_FFd2
	# rst & readData_reg<4> & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2
	# rst & phase1 & readData_reg<3> & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB8_12
	# rst & !phase1 & readData_reg<4>
	# rst & phase1 & readData_reg<3> & 
	inner_state_FFd4 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<3> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd3 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<3> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<3> & 
	!inner_state_FFd1 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB8_11
	# rst & readData_reg<4> & !main_state_FFd1
	# rst & readData_reg<4> & !i2c_state_FFd1;
   readData_reg<4>.CLK = clk;
    readData_reg<4>.EXP  =  !en<0> & !en<1>

MACROCELL | 7 | 10 | readData_reg<5>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 14 | 7 | 10 | 3 | 1 | 3 | 12 | 3 | 16 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 15 | 7 | 2 | 7 | 3 | 7 | 8 | 7 | 9 | 7 | 14 | 7 | 11
INPUTS | 12 | rst  | readData_reg<5>  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | phase1  | readData_reg<4>  | main_state_FFd1  | i2c_state_FFd1  | clk  | EXP38_.EXP
INPUTMC | 10 | 7 | 10 | 6 | 15 | 5 | 15 | 5 | 0 | 5 | 14 | 1 | 2 | 7 | 12 | 0 | 17 | 7 | 4 | 7 | 9
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 7 | 11
IMPORTS | 1 | 7 | 9
EQ | 27 | 
   readData_reg<5>.D = rst & readData_reg<5> & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2
	# rst & phase1 & readData_reg<4> & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB8_10
	# rst & readData_reg<5> & inner_state_FFd4 & 
	inner_state_FFd1 & inner_state_FFd2
	# rst & phase1 & readData_reg<4> & 
	inner_state_FFd4 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<4> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd3 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<4> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<4> & 
	!inner_state_FFd1 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB8_9
	# rst & !phase1 & readData_reg<5>
	# rst & readData_reg<5> & !main_state_FFd1
	# rst & readData_reg<5> & !i2c_state_FFd1;
   readData_reg<5>.CLK = clk;
    readData_reg<5>.EXP  =  rst & readData_reg<4> & !main_state_FFd1
	# rst & readData_reg<4> & !i2c_state_FFd1

MACROCELL | 7 | 1 | readData_reg<6>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 15 | 7 | 1 | 7 | 5 | 3 | 12 | 3 | 16 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 15 | 3 | 1 | 7 | 2 | 7 | 3 | 7 | 4 | 7 | 6 | 7 | 14 | 7 | 0
INPUTS | 12 | rst  | readData_reg<6>  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | phase1  | readData_reg<0>  | main_state_FFd1  | i2c_state_FFd1  | clk  | EXP35_.EXP
INPUTMC | 10 | 7 | 1 | 6 | 15 | 5 | 15 | 5 | 0 | 5 | 14 | 1 | 2 | 7 | 0 | 0 | 17 | 7 | 4 | 7 | 2
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 7 | 0
IMPORTS | 1 | 7 | 2
EQ | 28 | 
   readData_reg<6>.D = rst & readData_reg<6> & !inner_state_FFd4 & 
	!inner_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2
;Imported pterms FB8_3
	# rst & readData_reg<6> & inner_state_FFd4 & 
	inner_state_FFd1 & inner_state_FFd2
	# rst & phase1 & readData_reg<5> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd3 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<5> & 
	!inner_state_FFd4 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<5> & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# rst & phase1 & readData_reg<5> & 
	!inner_state_FFd1 & main_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB8_4
	# rst & !phase1 & readData_reg<6>
	# rst & readData_reg<6> & !main_state_FFd1
	# rst & readData_reg<6> & !i2c_state_FFd1
	# rst & phase1 & readData_reg<5> & 
	inner_state_FFd4 & main_state_FFd1 & !inner_state_FFd2 & 
	i2c_state_FFd1;
   readData_reg<6>.CLK = clk;
    readData_reg<6>.EXP  =  rst & !phase1 & readData_reg<0>
	# rst & readData_reg<0> & !main_state_FFd1
	# rst & readData_reg<0> & !i2c_state_FFd1

MACROCELL | 1 | 1 | phase2
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 3 | 1 | 1 | 6 | 12 | 6 | 11
INPUTS | 11 | rst  | phase2  | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk
INPUTMC | 9 | 1 | 1 | 1 | 4 | 1 | 13 | 1 | 17 | 1 | 12 | 1 | 11 | 1 | 16 | 1 | 15 | 1 | 10
INPUTP | 2 | 79 | 143
EQ | 4 | 
   phase2.D = rst & !phase2 & clk_div<0> & !clk_div<1> & 
	!clk_div<2> & !clk_div<3> & clk_div<4> & clk_div<5> & 
	!clk_div<6> & !clk_div<7>;
   phase2.CLK = clk;