📄 i2c.mfd
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!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> &
!cnt_delay<9> & start_delaycnt;
cnt_delay<8>.CLK = clk;
MACROCELL | 1 | 3 | phase0
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 8 | 6 | 6 | 1 | 3 | 6 | 12 | 2 | 13 | 6 | 5 | 6 | 8 | 6 | 9 | 6 | 11
INPUTS | 11 | rst | phase0 | clk_div<0> | clk_div<1> | clk_div<2> | clk_div<3> | clk_div<4> | clk_div<5> | clk_div<6> | clk_div<7> | clk
INPUTMC | 9 | 1 | 3 | 1 | 4 | 1 | 13 | 1 | 17 | 1 | 12 | 1 | 11 | 1 | 16 | 1 | 15 | 1 | 10
INPUTP | 2 | 79 | 143
EQ | 4 |
phase0.D = rst & !phase0 & clk_div<0> & clk_div<1> &
!clk_div<2> & !clk_div<3> & !clk_div<4> & clk_div<5> &
clk_div<6> & !clk_div<7>;
phase0.CLK = clk;
MACROCELL | 0 | 7 | cnt_delay<11>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 15 | rst | cnt_delay<0> | cnt_delay<10> | cnt_delay<8> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | start_delaycnt | cnt_delay<11> | clk
INPUTMC | 13 | 0 | 14 | 0 | 13 | 0 | 8 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 7
INPUTP | 2 | 79 | 143
EQ | 6 |
cnt_delay<11>.T = !rst & cnt_delay<11>
# rst & cnt_delay<0> & cnt_delay<10> &
cnt_delay<8> & cnt_delay<1> & cnt_delay<2> & cnt_delay<3> &
cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & cnt_delay<7> &
cnt_delay<9> & start_delaycnt;
cnt_delay<11>.CLK = clk;
MACROCELL | 0 | 6 | cnt_delay<14>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 14 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 18 | rst | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<8> | cnt_delay<11> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | start_delaycnt | cnt_delay<14> | clk
INPUTMC | 16 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 8 | 0 | 7 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 6
INPUTP | 2 | 79 | 143
EQ | 7 |
cnt_delay<14>.T = !rst & cnt_delay<14>
# rst & cnt_delay<0> & cnt_delay<10> &
cnt_delay<12> & cnt_delay<13> & cnt_delay<8> & cnt_delay<11> &
cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> &
cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9> &
start_delaycnt;
cnt_delay<14>.CLK = clk;
MACROCELL | 0 | 5 | cnt_delay<15>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 13 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 19 | rst | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | start_delaycnt | cnt_delay<15> | clk
INPUTMC | 17 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 8 | 0 | 7 | 0 | 6 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 5
INPUTP | 2 | 79 | 143
EQ | 7 |
cnt_delay<15>.T = !rst & cnt_delay<15>
# rst & cnt_delay<0> & cnt_delay<10> &
cnt_delay<12> & cnt_delay<13> & cnt_delay<8> & cnt_delay<11> &
cnt_delay<14> & cnt_delay<1> & cnt_delay<2> & cnt_delay<3> &
cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & cnt_delay<7> &
cnt_delay<9> & start_delaycnt;
cnt_delay<15>.CLK = clk;
MACROCELL | 0 | 4 | cnt_delay<16>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 12 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 20 | rst | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | start_delaycnt | cnt_delay<16> | clk
INPUTMC | 18 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 4
INPUTP | 2 | 79 | 143
EQ | 7 |
cnt_delay<16>.T = !rst & cnt_delay<16>
# rst & cnt_delay<0> & cnt_delay<10> &
cnt_delay<12> & cnt_delay<13> & cnt_delay<8> & cnt_delay<11> &
cnt_delay<14> & cnt_delay<15> & cnt_delay<1> & cnt_delay<2> &
cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> &
cnt_delay<7> & cnt_delay<9> & start_delaycnt;
cnt_delay<16>.CLK = clk;
MACROCELL | 0 | 3 | cnt_delay<17>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 11 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 3 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 21 | rst | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<16> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | start_delaycnt | cnt_delay<17> | clk
INPUTMC | 19 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 3
INPUTP | 2 | 79 | 143
EQ | 7 |
cnt_delay<17>.T = !rst & cnt_delay<17>
# rst & cnt_delay<0> & cnt_delay<10> &
cnt_delay<12> & cnt_delay<13> & cnt_delay<8> & cnt_delay<11> &
cnt_delay<14> & cnt_delay<15> & cnt_delay<16> & cnt_delay<1> &
cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> &
cnt_delay<6> & cnt_delay<7> & cnt_delay<9> & start_delaycnt;
cnt_delay<17>.CLK = clk;
MACROCELL | 0 | 9 | cnt_delay<19>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 10 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 23 | rst | cnt_delay<19> | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<18> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<16> | cnt_delay<17> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | start_delaycnt | clk
INPUTMC | 21 | 0 | 9 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15
INPUTP | 2 | 79 | 143
EQ | 14 |
cnt_delay<19>.T = !rst & cnt_delay<19>
# rst & cnt_delay<0> & cnt_delay<10> &
cnt_delay<12> & cnt_delay<13> & cnt_delay<18> & cnt_delay<8> &
cnt_delay<11> & cnt_delay<14> & cnt_delay<15> & cnt_delay<16> &
cnt_delay<17> & cnt_delay<1> & cnt_delay<2> & cnt_delay<3> &
cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & cnt_delay<7> &
cnt_delay<9> & start_delaycnt
# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> &
!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> &
cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> &
!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> &
!cnt_delay<9> & start_delaycnt;
cnt_delay<19>.CLK = clk;
MACROCELL | 1 | 9 | cnt_delay<1>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 22 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 5 | rst | cnt_delay<0> | start_delaycnt | cnt_delay<1> | clk
INPUTMC | 3 | 0 | 14 | 0 | 15 | 1 | 9
INPUTP | 2 | 79 | 143
EQ | 3 |
cnt_delay<1>.T = !rst & cnt_delay<1>
# rst & cnt_delay<0> & start_delaycnt;
cnt_delay<1>.CLK = clk;
MACROCELL | 1 | 8 | cnt_delay<2>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 21 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 6 | rst | cnt_delay<0> | cnt_delay<1> | start_delaycnt | cnt_delay<2> | clk
INPUTMC | 4 | 0 | 14 | 1 | 9 | 0 | 15 | 1 | 8
INPUTP | 2 | 79 | 143
EQ | 4 |
cnt_delay<2>.T = !rst & cnt_delay<2>
# rst & cnt_delay<0> & cnt_delay<1> &
start_delaycnt;
cnt_delay<2>.CLK = clk;
MACROCELL | 1 | 7 | cnt_delay<3>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 20 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 7 | rst | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | start_delaycnt | cnt_delay<3> | clk
INPUTMC | 5 | 0 | 14 | 1 | 9 | 1 | 8 | 0 | 15 | 1 | 7
INPUTP | 2 | 79 | 143
EQ | 4 |
cnt_delay<3>.T = !rst & cnt_delay<3>
# rst & cnt_delay<0> & cnt_delay<1> &
cnt_delay<2> & start_delaycnt;
cnt_delay<3>.CLK = clk;
MACROCELL | 1 | 6 | cnt_delay<4>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 19 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 8 | rst | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | start_delaycnt | cnt_delay<4> | clk
INPUTMC | 6 | 0 | 14 | 1 | 9 | 1 | 8 | 1 | 7 | 0 | 15 | 1 | 6
INPUTP | 2 | 79 | 143
EQ | 4 |
cnt_delay<4>.T = !rst & cnt_delay<4>
# rst & cnt_delay<0> & cnt_delay<1> &
cnt_delay<2> & cnt_delay<3> & start_delaycnt;
cnt_delay<4>.CLK = clk;
MACROCELL | 1 | 5 | cnt_delay<5>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 18 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 9 | rst | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | start_delaycnt | cnt_delay<5> | clk
INPUTMC | 7 | 0 | 14 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 0 | 15 | 1 | 5
INPUTP | 2 | 79 | 143
EQ | 4 |
cnt_delay<5>.T = !rst & cnt_delay<5>
# rst & cnt_delay<0> & cnt_delay<1> &
cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & start_delaycnt;
cnt_delay<5>.CLK = clk;
MACROCELL | 0 | 2 | cnt_delay<6>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 17 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 10 | rst | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | start_delaycnt | cnt_delay<6> | clk
INPUTMC | 8 | 0 | 14 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 15 | 0 | 2
INPUTP | 2 | 79 | 143
EQ | 5 |
cnt_delay<6>.T = !rst & cnt_delay<6>
# rst & cnt_delay<0> & cnt_delay<1> &
cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> &
start_delaycnt;
cnt_delay<6>.CLK = clk;
MACROCELL | 0 | 1 | cnt_delay<7>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 16 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 11 | rst | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | start_delaycnt | cnt_delay<7> | clk
INPUTMC | 9 | 0 | 14 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 15 | 0 | 1
INPUTP | 2 | 79 | 143
EQ | 5 |
cnt_delay<7>.T = !rst & cnt_delay<7>
# rst & cnt_delay<0> & cnt_delay<1> &
cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> &
cnt_delay<6> & start_delaycnt;
cnt_delay<7>.CLK = clk;
MACROCELL | 0 | 0 | cnt_delay<9>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 34 | rst | cnt_delay<0> | cnt_delay<8> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | start_delaycnt | cnt_delay<9> | clk | sda | phase1 | inner_state_FFd4 | inner_state_FFd1 | main_state_FFd1 | inner_state_FFd3 | i2c_state_FFd2 | i2c_state_FFd1 | rd_input | wr_input | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<18> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<16> | cnt_delay<17> | cnt_delay<19> | main_state_FFd2
INPUTMC | 30 | 0 | 14 | 0 | 8 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 15 | 0 | 0 | 6 | 7 | 1 | 2 | 6 | 15 | 5 | 15 | 0 | 17 | 5 | 0 | 6 | 13 | 7 | 4 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 16
INPUTP | 4 | 79 | 143 | 109 | 112
EXPORTS | 1 | 0 | 17
EQ | 15 |
cnt_delay<9>.T = !rst & cnt_delay<9>
# rst & cnt_delay<0> & cnt_delay<8> &
cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> &
cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & start_delaycnt;
cnt_delay<9>.CLK = clk;
cnt_delay<9>.EXP = sda & phase1 & inner_state_FFd4 &
inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 &
!i2c_state_FFd2 & !i2c_state_FFd1
# !rd_input & rst & wr_input & !cnt_delay<0> &
cnt_delay<10> & cnt_delay<12> & cnt_delay<13> & cnt_delay<18> &
cnt_delay<8> & !cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> &
!cnt_delay<16> & !cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> &
!cnt_delay<2> & !cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> &
!cnt_delay<6> & !cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 &
!main_state_FFd2
MACROCELL | 7 | 0 | readData_reg<0>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 14 | 7 | 0 | 5 | 12 | 3 | 0 | 3 | 15 | 5 | 8 | 3 | 12 | 5 | 2 | 7 | 15 | 3 | 10 | 3 | 14 | 3 | 17 | 5 | 11 | 7 | 1 | 7 | 14
INPUTS | 13 | rst | readData_reg<0> | inner_state_FFd4 | inner_state_FFd1 | inner_state_FFd3 | inner_state_FFd2 | sda.PIN | phase1 | main_state_FFd1 | i2c_state_FFd1 | clk | readData_reg<6>.EXP | readData_reg<3>.EXP
INPUTMC | 10 | 7 | 0 | 6 | 15 | 5 | 15 | 5 | 0 | 5 | 14 | 1 | 2 | 0 | 17 | 7 | 4 | 7 | 1 | 7 | 17
INPUTP | 3 | 79 | 88 | 143
IMPORTS | 2 | 7 | 1 | 7 | 17
EQ | 20 |
readData_reg<0>.D = rst & readData_reg<0> & inner_state_FFd4 &
inner_state_FFd1 & inner_state_FFd2
# rst & readData_reg<0> & !inner_state_FFd4 &
!inner_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2
# rst & sda.PIN & phase1 & inner_state_FFd1 &
main_state_FFd1 & !inner_state_FFd2 & i2c_state_FFd1
# rst & sda.PIN & phase1 & !inner_state_FFd1 &
main_state_FFd1 & inner_state_FFd2 & i2c_state_FFd1
;Imported pterms FB8_2
# rst & !phase1 & readData_reg<0>
# rst & readData_reg<0> & !main_state_FFd1
# rst & readData_reg<0> & !i2c_state_FFd1
;Imported pterms FB8_18
# rst & sda.PIN & phase1 & inner_state_FFd4 &
main_state_FFd1 & !inner_state_FFd2 & i2c_state_FFd1
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