i2c.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

MDF Database:  version 1.0
MDF_INFO | i2c | XC95144XL-10-TQ144
MACROCELL | 6 | 7 | sda_buf
ATTRIBUTES | 8783650 | 0
OUTPUTMC | 11 | 6 | 7 | 0 | 17 | 0 | 16 | 4 | 17 | 2 | 13 | 0 | 0 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 9 | 6 | 10
INPUTS | 11 | rst  | main_state_FFd1  | main_state_FFd2  | sda  | inner_state_FFd3  | inner_state_FFd2  | $OpTx$$OpTx$FX_DC$40_INV$388  | EXP28_.EXP  | EXP29_.EXP  | clk  | link
INPUTMC | 9 | 0 | 17 | 0 | 16 | 6 | 7 | 5 | 0 | 5 | 14 | 2 | 2 | 6 | 6 | 6 | 8 | 6 | 2
INPUTP | 2 | 79 | 143
IMPORTS | 2 | 6 | 6 | 6 | 8
EQ | 56 | 
   sda.D = !rst
	# !main_state_FFd1 & !main_state_FFd2
	# sda & inner_state_FFd3 & inner_state_FFd2 & 
	$OpTx$$OpTx$FX_DC$40_INV$388
;Imported pterms FB7_7
	# sda & !phase3 & !phase0 & inner_state_FFd2
	# sda & !phase3 & !$OpTx$$OpTx$FX_DC$38_INV$387 & 
	!$OpTx$$OpTx$FX_DC$62_INV$392
	# sda & main_state_FFd2 & i2c_state_FFd2 & 
	!$OpTx$$OpTx$FX_DC$63_INV$393
	# sda & i2c_state_FFd3 & !i2c_state_FFd1 & 
	$OpTx$$OpTx$FX_DC$44_INV$389
	# phase1 & main_state_FFd2 & i2c_state_FFd2 & 
	$OpTx$FX_DC$67
;Imported pterms FB7_6
	# sda & !phase3 & main_state_FFd2 & i2c_state_FFd2 & 
	!$OpTx$$OpTx$FX_DC$53_INV$390
	# sda.PIN & phase0 & main_state_FFd1 & 
	i2c_state_FFd1 & !$OpTx$$OpTx$FX_DC$69_INV$394
	# sda.PIN & phase0 & !inner_state_FFd3 & 
	$OpTx$$OpTx$FX_DC$40_INV$388 & $OpTx$FX_DC$60
	# phase3 & !inner_state_FFd1 & inner_state_FFd2 & 
	i2c_state_FFd3 & $OpTx$FX_DC$70
	# inner_state_FFd1 & main_state_FFd1 & 
	inner_state_FFd3 & i2c_state_FFd1 & !$OpTx$$OpTx$FX_DC$54_INV$391
;Imported pterms FB7_9
	# sda & !phase3 & main_state_FFd1 & i2c_state_FFd1 & 
	$OpTx$$OpTx$FX_DC$40_INV$388
	# sda & !phase0 & main_state_FFd1 & 
	!inner_state_FFd2 & i2c_state_FFd1
	# sda & !phase0 & main_state_FFd1 & i2c_state_FFd1 & 
	!$OpTx$$OpTx$FX_DC$40_INV$388
	# sda & !inner_state_FFd4 & !inner_state_FFd3 & 
	$OpTx$$OpTx$FX_DC$53_INV$390 & !$OpTx$$OpTx$FX_DC$38_INV$387
	# phase3 & !inner_state_FFd2 & !i2c_state_FFd3 & 
	$OpTx$FX_DC$41 & $OpTx$FX_DC$59
;Imported pterms FB7_10
	# sda & !phase1 & !inner_state_FFd4 & 
	!inner_state_FFd3 & !inner_state_FFd2 & !$OpTx$$OpTx$FX_DC$38_INV$387
	# sda & !phase0 & !main_state_FFd2 & i2c_state_FFd2 & 
	!i2c_state_FFd1 & $OpTx$$OpTx$FX_DC$40_INV$388
	# sda & !inner_state_FFd4 & !inner_state_FFd3 & 
	!inner_state_FFd2 & i2c_state_FFd3 & !$OpTx$$OpTx$FX_DC$44_INV$389
	# phase3 & !inner_state_FFd4 & inner_state_FFd3 & 
	inner_state_FFd2 & i2c_state_FFd3 & $OpTx$FX_DC$48
	# phase3 & main_state_FFd1 & !inner_state_FFd3 & 
	i2c_state_FFd3 & !i2c_state_FFd2 & $OpTx$$OpTx$FX_DC$40_INV$388
;Imported pterms FB7_11
	# sda & !inner_state_FFd4 & !inner_state_FFd1 & 
	main_state_FFd1 & !inner_state_FFd3 & !inner_state_FFd2 & 
	i2c_state_FFd1
	# phase3 & !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & inner_state_FFd2 & !i2c_state_FFd3 & 
	!i2c_state_FFd1 & $OpTx$$OpTx$FX_DC$44_INV$389;
   sda.CLK = clk;
   sda.OE = link;

MACROCELL | 3 | 10 | en_0
ATTRIBUTES | 4588322 | 0
OUTPUTMC | 18 | 3 | 9 | 3 | 12 | 3 | 16 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 15 | 3 | 2 | 3 | 10 | 3 | 11 | 3 | 14 | 3 | 15 | 3 | 17 | 5 | 2 | 5 | 8 | 7 | 12 | 7 | 13 | 7 | 14
INPUTS | 8 | en<0>  | en<1>  | readData_reg<0>  | readData_reg<1>  | readData_reg<2>  | readData_reg<3>  | cnt_scan<10>.EXP  | clk
INPUTMC | 7 | 3 | 10 | 3 | 8 | 7 | 0 | 5 | 12 | 5 | 5 | 7 | 17 | 3 | 9
INPUTP | 1 | 143
EXPORTS | 1 | 3 | 11
IMPORTS | 1 | 3 | 9
EQ | 15 | 
   en<0>.T = ;Imported pterms FB4_10
	  !rst & en<0>
	# rst & cnt_scan<0> & cnt_scan<10> & cnt_scan<1> & 
	cnt_scan<2> & cnt_scan<3> & cnt_scan<4> & cnt_scan<5> & 
	cnt_scan<6> & cnt_scan<7> & cnt_scan<8> & cnt_scan<9> & 
	cnt_scan<11>;
   en<0>.CLK = clk;
    en_0.EXP  =  en<0> & !en<1> & readData_reg<0> & 
	readData_reg<1> & !readData_reg<2> & readData_reg<3>
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<1> & readData_reg<2> & readData_reg<3>
	# en<0> & !en<1> & readData_reg<0> & 
	!readData_reg<1> & !readData_reg<2> & !readData_reg<3>
	# en<0> & !en<1> & !readData_reg<0> & 
	!readData_reg<1> & readData_reg<2> & !readData_reg<3>

MACROCELL | 3 | 8 | en_1
ATTRIBUTES | 4588322 | 0
OUTPUTMC | 18 | 3 | 8 | 3 | 0 | 3 | 16 | 5 | 9 | 3 | 13 | 5 | 3 | 7 | 13 | 3 | 12 | 3 | 1 | 3 | 2 | 3 | 10 | 3 | 11 | 3 | 14 | 3 | 15 | 3 | 17 | 5 | 2 | 5 | 8 | 7 | 12
INPUTS | 15 | rst  | en<1>  | cnt_scan<0>  | cnt_scan<10>  | cnt_scan<1>  | cnt_scan<2>  | cnt_scan<3>  | cnt_scan<4>  | cnt_scan<5>  | cnt_scan<6>  | cnt_scan<7>  | cnt_scan<8>  | cnt_scan<9>  | cnt_scan<11>  | clk
INPUTMC | 13 | 3 | 8 | 2 | 4 | 3 | 9 | 2 | 12 | 2 | 11 | 2 | 10 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 2 | 3 | 17 | 3 | 7
INPUTP | 2 | 79 | 143
EQ | 6 | 
   en<1>.T = !rst & !en<1>
	# rst & cnt_scan<0> & cnt_scan<10> & cnt_scan<1> & 
	cnt_scan<2> & cnt_scan<3> & cnt_scan<4> & cnt_scan<5> & 
	cnt_scan<6> & cnt_scan<7> & cnt_scan<8> & cnt_scan<9> & 
	cnt_scan<11>;
   en<1>.CLK = clk;

MACROCELL | 1 | 0 | phase3
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 27 | 6 | 6 | 1 | 0 | 6 | 15 | 5 | 15 | 0 | 17 | 5 | 0 | 5 | 13 | 0 | 16 | 7 | 7 | 6 | 12 | 7 | 4 | 5 | 17 | 2 | 14 | 5 | 1 | 5 | 12 | 5 | 14 | 5 | 16 | 6 | 3 | 6 | 4 | 6 | 5 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 14 | 6 | 16 | 6 | 17
INPUTS | 11 | rst  | phase3  | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk
INPUTMC | 9 | 1 | 0 | 1 | 4 | 1 | 13 | 1 | 17 | 1 | 12 | 1 | 11 | 1 | 16 | 1 | 15 | 1 | 10
INPUTP | 2 | 79 | 143
EQ | 4 | 
   phase3.D = rst & !phase3 & !clk_div<0> & clk_div<1> & 
	!clk_div<2> & clk_div<3> & !clk_div<4> & !clk_div<5> & 
	clk_div<6> & !clk_div<7>;
   phase3.CLK = clk;

MACROCELL | 1 | 2 | phase1
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 31 | 6 | 6 | 1 | 2 | 7 | 0 | 5 | 12 | 5 | 5 | 7 | 16 | 7 | 12 | 7 | 10 | 6 | 9 | 7 | 5 | 0 | 17 | 0 | 0 | 0 | 16 | 6 | 2 | 4 | 17 | 5 | 1 | 5 | 4 | 5 | 10 | 5 | 11 | 6 | 0 | 6 | 1 | 7 | 1 | 7 | 2 | 7 | 3 | 7 | 4 | 7 | 6 | 7 | 8 | 7 | 9 | 7 | 11 | 7 | 15 | 7 | 17
INPUTS | 11 | rst  | phase1  | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk
INPUTMC | 9 | 1 | 2 | 1 | 4 | 1 | 13 | 1 | 17 | 1 | 12 | 1 | 11 | 1 | 16 | 1 | 15 | 1 | 10
INPUTP | 2 | 79 | 143
EQ | 4 | 
   phase1.D = rst & !phase1 & !clk_div<0> & !clk_div<1> & 
	!clk_div<2> & clk_div<3> & clk_div<4> & !clk_div<5> & 
	!clk_div<6> & !clk_div<7>;
   phase1.CLK = clk;

MACROCELL | 0 | 14 | cnt_delay<0>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 22 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | rst  | start_delaycnt  | clk
INPUTMC | 21 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15
INPUTP | 2 | 79 | 143
EQ | 9 | 
   !cnt_delay<0>.T = rst & !start_delaycnt
	# !rst & !cnt_delay<0>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<0>.CLK = clk;

MACROCELL | 0 | 13 | cnt_delay<10>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 23 | rst  | cnt_delay<10>  | cnt_delay<0>  | cnt_delay<8>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk
INPUTMC | 21 | 0 | 13 | 0 | 14 | 0 | 8 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9
INPUTP | 2 | 79 | 143
EQ | 12 | 
   cnt_delay<10>.T = !rst & cnt_delay<10>
	# rst & cnt_delay<0> & cnt_delay<8> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9> & 
	start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<10>.CLK = clk;

MACROCELL | 0 | 12 | cnt_delay<12>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 14 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 23 | rst  | cnt_delay<12>  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk
INPUTMC | 21 | 0 | 12 | 0 | 14 | 0 | 13 | 0 | 8 | 0 | 7 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 11 | 0 | 10 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9
INPUTP | 2 | 79 | 143
EQ | 12 | 
   cnt_delay<12>.T = !rst & cnt_delay<12>
	# rst & cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<8> & cnt_delay<11> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & 
	cnt_delay<7> & cnt_delay<9> & start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<12>.CLK = clk;

MACROCELL | 0 | 11 | cnt_delay<13>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 14 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 23 | rst  | cnt_delay<13>  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<18>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk
INPUTMC | 21 | 0 | 11 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 8 | 0 | 7 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 10 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9
INPUTP | 2 | 79 | 143
EQ | 12 | 
   cnt_delay<13>.T = !rst & cnt_delay<13>
	# rst & cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<8> & cnt_delay<11> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7> & cnt_delay<9> & start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<13>.CLK = clk;

MACROCELL | 0 | 10 | cnt_delay<18>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 10 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 9 | 0 | 15 | 0 | 0 | 0 | 17
INPUTS | 23 | rst  | cnt_delay<18>  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<19>  | clk
INPUTMC | 21 | 0 | 10 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 9
INPUTP | 2 | 79 | 143
EQ | 14 | 
   cnt_delay<18>.T = !rst & cnt_delay<18>
	# rst & cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & 
	cnt_delay<14> & cnt_delay<15> & cnt_delay<16> & cnt_delay<17> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9> & 
	start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<18>.CLK = clk;

MACROCELL | 0 | 8 | cnt_delay<8>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 8 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 0 | 0 | 15 | 0 | 17
INPUTS | 23 | rst  | cnt_delay<8>  | cnt_delay<0>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | start_delaycnt  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<9>  | clk
INPUTMC | 21 | 0 | 8 | 0 | 14 | 1 | 9 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 0 | 2 | 0 | 1 | 0 | 15 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7 | 0 | 6 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 9 | 0 | 0
INPUTP | 2 | 79 | 143
EQ | 11 | 
   cnt_delay<8>.T = !rst & cnt_delay<8>
	# rst & cnt_delay<0> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7> & start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> &