i2c.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\temp\spartan2\veriloge\interface\iic\iic\IIC.ise -intstyle ise -e 3 -l 3 -s
6 -xml i2c i2c.ncd -o i2c.twr i2c.pcf


Design file:              i2c.ncd
Physical constraint file: i2c.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
data_in<0>  |    2.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
data_in<1>  |    2.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
data_in<2>  |    2.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
data_in<3>  |    2.200(R)|    0.000(R)|clk_BUFGP         |   0.000|
rd_input    |    5.989(R)|   -1.319(R)|clk_BUFGP         |   0.000|
rst         |    5.416(R)|   -0.128(R)|clk_BUFGP         |   0.000|
sda         |    8.194(R)|   -2.277(R)|clk_BUFGP         |   0.000|
wr_input    |    5.927(R)|   -1.196(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
en<0>       |    9.738(R)|clk_BUFGP         |   0.000|
en<1>       |   10.616(R)|clk_BUFGP         |   0.000|
scl         |   10.006(R)|clk_BUFGP         |   0.000|
sda         |   10.274(R)|clk_BUFGP         |   0.000|
seg_data<1> |   14.933(R)|clk_BUFGP         |   0.000|
seg_data<2> |   14.960(R)|clk_BUFGP         |   0.000|
seg_data<3> |   15.605(R)|clk_BUFGP         |   0.000|
seg_data<4> |   15.888(R)|clk_BUFGP         |   0.000|
seg_data<5> |   15.448(R)|clk_BUFGP         |   0.000|
seg_data<6> |   15.738(R)|clk_BUFGP         |   0.000|
seg_data<7> |   15.734(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    9.681|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Mar 14 15:18:11 2006
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Peak Memory Usage: 65 MB