i2c.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

	OR (rst AND cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND 
	cnt_scan(7)));

FTCPE_cnt_scan9: FTCPE port map (cnt_scan(9),cnt_scan_T(9),clk,'0','0');
cnt_scan_T(9) <= ((NOT rst AND cnt_scan(9))
	OR (rst AND cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND 
	cnt_scan(7) AND cnt_scan(8)));

FTCPE_cnt_scan10: FTCPE port map (cnt_scan(10),cnt_scan_T(10),clk,'0','0');
cnt_scan_T(10) <= ((NOT rst AND cnt_scan(10))
	OR (rst AND cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND 
	cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6) AND 
	cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9)));

FTCPE_cnt_scan11: FTCPE port map (cnt_scan(11),cnt_scan_T(11),clk,'0','0');
cnt_scan_T(11) <= ((NOT rst AND cnt_scan(11))
	OR (rst AND cnt_scan(0) AND cnt_scan(10) AND cnt_scan(1) AND 
	cnt_scan(2) AND cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND 
	cnt_scan(6) AND cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9)));

FTCPE_en0: FTCPE port map (en(0),cnt_scan(10).EXP,clk,'0','0');

FTCPE_en1: FTCPE port map (en(1),en_T(1),clk,'0','0');
en_T(1) <= ((NOT rst AND NOT en(1))
	OR (rst AND cnt_scan(0) AND cnt_scan(10) AND cnt_scan(1) AND 
	cnt_scan(2) AND cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND 
	cnt_scan(6) AND cnt_scan(7) AND cnt_scan(8) AND cnt_scan(9) AND 
	cnt_scan(11)));

FDCPE_i2c_state_FFd1: FDCPE port map (i2c_state_FFd1,i2c_state_FFd1_D,clk,'0','0');
i2c_state_FFd1_D <= ((rst AND main_state_FFd1 AND i2c_state_FFd1)
	OR (rst AND main_state_FFd2 AND i2c_state_FFd1)
	OR (rst AND phase3 AND inner_state_FFd4 AND 
	inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd3 AND 
	NOT i2c_state_FFd3 AND i2c_state_FFd2));

FDCPE_i2c_state_FFd2: FDCPE port map (i2c_state_FFd2,i2c_state_FFd2_D,clk,'0','0');
i2c_state_FFd2_D <= ((scl_OBUF.EXP)
	OR (rst AND main_state_FFd1 AND i2c_state_FFd2)
	OR (rst AND main_state_FFd2 AND i2c_state_FFd2));

FTCPE_i2c_state_FFd3: FTCPE port map (i2c_state_FFd3,i2c_state_FFd3_T,clk,'0','0');
i2c_state_FFd3_T <= ((lowbit_OBUF.EXP)
	OR (NOT rst AND i2c_state_FFd3));

FTCPE_inner_state_FFd1: FTCPE port map (inner_state_FFd1,inner_state_FFd1_T,clk,'0','0');
inner_state_FFd1_T <= ((inner_state_FFd2.EXP)
	OR (EXP21_.EXP)
	OR (rst AND phase3 AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd3 AND 
	inner_state_FFd2 AND NOT i2c_state_FFd3)
	OR (rst AND phase3 AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd3 AND 
	inner_state_FFd2 AND i2c_state_FFd1)
	OR (rst AND phase3 AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND inner_state_FFd2 AND 
	main_state_FFd2 AND i2c_state_FFd3)
	OR (rst AND phase3 AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND inner_state_FFd2 AND 
	main_state_FFd2 AND NOT i2c_state_FFd2));

FDCPE_inner_state_FFd2: FDCPE port map (inner_state_FFd2,inner_state_FFd2_D,clk,'0','0');
inner_state_FFd2_D <= ((NOT rst)
	OR (EXP20_.EXP)
	OR (NOT main_state_FFd1 AND NOT main_state_FFd2)
	OR (inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	NOT inner_state_FFd2));

FTCPE_inner_state_FFd3: FTCPE port map (inner_state_FFd3,inner_state_FFd3_T,clk,'0','0');
inner_state_FFd3_T <= ((_10_.EXP)
	OR (EXP22_.EXP)
	OR (NOT rst AND inner_state_FFd3)
	OR (NOT main_state_FFd1 AND inner_state_FFd3 AND 
	NOT main_state_FFd2)
	OR (phase3 AND inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	inner_state_FFd3 AND inner_state_FFd2 AND NOT i2c_state_FFd2)
	OR (phase3 AND inner_state_FFd4 AND NOT inner_state_FFd1 AND 
	inner_state_FFd3 AND inner_state_FFd2 AND NOT main_state_FFd2 AND 
	NOT i2c_state_FFd3));

FDCPE_inner_state_FFd4: FDCPE port map (inner_state_FFd4,inner_state_FFd4_D,clk,'0','0');
inner_state_FFd4_D <= ((EXP32_.EXP)
	OR (EXP33_.EXP)
	OR (rst AND NOT phase3 AND inner_state_FFd4 AND 
	main_state_FFd1)
	OR (rst AND NOT phase3 AND inner_state_FFd4 AND 
	main_state_FFd2)
	OR (rst AND inner_state_FFd1 AND main_state_FFd1 AND 
	inner_state_FFd3)
	OR (rst AND inner_state_FFd1 AND inner_state_FFd3 AND 
	main_state_FFd2));

FDCPE_link: FDCPE port map (link,link_D,clk,'0','0');
link_D <= ((EXP24_.EXP)
	OR (EXP25_.EXP)
	OR (inner_state_FFd3 AND NOT i2c_state_FFd3 AND 
	i2c_state_FFd2 AND i2c_state_FFd1 AND NOT link)
	OR (NOT main_state_FFd2 AND i2c_state_FFd3 AND 
	i2c_state_FFd2 AND NOT i2c_state_FFd1 AND NOT link)
	OR (phase1 AND inner_state_FFd1 AND NOT main_state_FFd1 AND 
	NOT inner_state_FFd3 AND inner_state_FFd2 AND i2c_state_FFd2 AND NOT link)
	OR (inner_state_FFd1 AND NOT inner_state_FFd3 AND 
	inner_state_FFd2 AND NOT i2c_state_FFd3 AND i2c_state_FFd2 AND NOT i2c_state_FFd1 AND 
	NOT link));


lowbit <= '0';

FTCPE_main_state_FFd1: FTCPE port map (main_state_FFd1,main_state_FFd1_T,clk,'0','0');
main_state_FFd1_T <= ((cnt_delay(9).EXP)
	OR (NOT rst AND main_state_FFd1)
	OR (phase3 AND inner_state_FFd1 AND main_state_FFd1 AND 
	inner_state_FFd3 AND i2c_state_FFd2 AND i2c_state_FFd1)
	OR (sda AND phase1 AND inner_state_FFd4 AND 
	inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd3 AND 
	NOT i2c_state_FFd3 AND NOT i2c_state_FFd1));

FTCPE_main_state_FFd2: FTCPE port map (main_state_FFd2,main_state_FFd2_T,clk,'0','0');
main_state_FFd2_T <= ((main_state_FFd1.EXP)
	OR (NOT rst AND main_state_FFd2)
	OR (main_state_FFd2 AND NOT i2c_state_FFd3 AND 
	i2c_state_FFd2)
	OR (phase3 AND inner_state_FFd1 AND inner_state_FFd3 AND 
	main_state_FFd2 AND i2c_state_FFd2)
	OR (sda AND phase1 AND inner_state_FFd4 AND 
	inner_state_FFd1 AND NOT inner_state_FFd3 AND main_state_FFd2));

FDCPE_phase0: FDCPE port map (phase0,phase0_D,clk,'0','0');
phase0_D <= (rst AND NOT phase0 AND clk_div(0) AND clk_div(1) AND 
	NOT clk_div(2) AND NOT clk_div(3) AND NOT clk_div(4) AND clk_div(5) AND 
	clk_div(6) AND NOT clk_div(7));

FDCPE_phase1: FDCPE port map (phase1,phase1_D,clk,'0','0');
phase1_D <= (rst AND NOT phase1 AND NOT clk_div(0) AND NOT clk_div(1) AND 
	NOT clk_div(2) AND clk_div(3) AND clk_div(4) AND NOT clk_div(5) AND 
	NOT clk_div(6) AND NOT clk_div(7));

FDCPE_phase2: FDCPE port map (phase2,phase2_D,clk,'0','0');
phase2_D <= (rst AND NOT phase2 AND clk_div(0) AND NOT clk_div(1) AND 
	NOT clk_div(2) AND NOT clk_div(3) AND clk_div(4) AND clk_div(5) AND 
	NOT clk_div(6) AND NOT clk_div(7));

FDCPE_phase3: FDCPE port map (phase3,phase3_D,clk,'0','0');
phase3_D <= (rst AND NOT phase3 AND NOT clk_div(0) AND clk_div(1) AND 
	NOT clk_div(2) AND clk_div(3) AND NOT clk_div(4) AND NOT clk_div(5) AND 
	clk_div(6) AND NOT clk_div(7));

FDCPE_readData_reg0: FDCPE port map (readData_reg(0),readData_reg_D(0),clk,'0','0');
readData_reg_D(0) <= ((readData_reg(6).EXP)
	OR (readData_reg(3).EXP)
	OR (rst AND readData_reg(0) AND inner_state_FFd4 AND 
	inner_state_FFd1 AND inner_state_FFd2)
	OR (rst AND readData_reg(0) AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND NOT inner_state_FFd2)
	OR (rst AND sda.PIN AND phase1 AND inner_state_FFd1 AND 
	main_state_FFd1 AND NOT inner_state_FFd2 AND i2c_state_FFd1)
	OR (rst AND sda.PIN AND phase1 AND NOT inner_state_FFd1 AND 
	main_state_FFd1 AND inner_state_FFd2 AND i2c_state_FFd1));

FDCPE_readData_reg1: FDCPE port map (readData_reg(1),readData_reg_D(1),clk,'0','0');
readData_reg_D(1) <= ((EXP19_.EXP)
	OR (rst AND readData_reg(1) AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND NOT inner_state_FFd2)
	OR (rst AND phase1 AND readData_reg(0) AND 
	inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd2 AND 
	i2c_state_FFd1));

FDCPE_readData_reg2: FDCPE port map (readData_reg(2),readData_reg_D(2),clk,'0','0');
readData_reg_D(2) <= ((EXP18_.EXP)
	OR ($OpTx$FX_DC$70.EXP)
	OR (rst AND readData_reg(2) AND inner_state_FFd4 AND 
	inner_state_FFd1 AND inner_state_FFd2)
	OR (rst AND readData_reg(2) AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND NOT inner_state_FFd2)
	OR (rst AND phase1 AND readData_reg(1) AND 
	inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd2 AND 
	i2c_state_FFd1)
	OR (rst AND phase1 AND readData_reg(1) AND 
	NOT inner_state_FFd1 AND main_state_FFd1 AND inner_state_FFd2 AND 
	i2c_state_FFd1));

FDCPE_readData_reg3: FDCPE port map (readData_reg(3),readData_reg_D(3),clk,'0','0');
readData_reg_D(3) <= ((EXP42_.EXP)
	OR (rst AND readData_reg(3) AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND NOT inner_state_FFd2));

FDCPE_readData_reg4: FDCPE port map (readData_reg(4),readData_reg_D(4),clk,'0','0');
readData_reg_D(4) <= ((EXP39_.EXP)
	OR (rst AND readData_reg(4) AND inner_state_FFd4 AND 
	inner_state_FFd1 AND inner_state_FFd2)
	OR (rst AND readData_reg(4) AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND NOT inner_state_FFd2)
	OR (rst AND phase1 AND readData_reg(3) AND 
	inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd2 AND 
	i2c_state_FFd1));

FDCPE_readData_reg5: FDCPE port map (readData_reg(5),readData_reg_D(5),clk,'0','0');
readData_reg_D(5) <= ((EXP38_.EXP)
	OR (rst AND readData_reg(5) AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND NOT inner_state_FFd2)
	OR (rst AND phase1 AND readData_reg(4) AND 
	inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd2 AND 
	i2c_state_FFd1));

FDCPE_readData_reg6: FDCPE port map (readData_reg(6),readData_reg_D(6),clk,'0','0');
readData_reg_D(6) <= ((EXP35_.EXP)
	OR (rst AND readData_reg(6) AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND NOT inner_state_FFd2));

FDCPE_readData_reg7: FDCPE port map (readData_reg(7),readData_reg_D(7),clk,'0','0');
readData_reg_D(7) <= ((i2c_state_FFd1.EXP)
	OR (EXP37_.EXP)
	OR (rst AND readData_reg(7) AND inner_state_FFd4 AND 
	inner_state_FFd1 AND inner_state_FFd2)
	OR (rst AND readData_reg(7) AND NOT inner_state_FFd4 AND 
	NOT inner_state_FFd1 AND NOT inner_state_FFd3 AND NOT inner_state_FFd2)
	OR (rst AND phase1 AND readData_reg(6) AND 
	inner_state_FFd1 AND main_state_FFd1 AND NOT inner_state_FFd2 AND 
	i2c_state_FFd1)
	OR (rst AND phase1 AND readData_reg(6) AND 
	NOT inner_state_FFd1 AND main_state_FFd1 AND inner_state_FFd2 AND 
	i2c_state_FFd1));

FDCPE_scl: FDCPE port map (scl,scl_D,clk,'0','0');
scl_D <= ((EXP31_.EXP)
	OR (rst AND NOT phase0 AND phase2 AND main_state_FFd1));

FDCPE_sda: FDCPE port map (sda_I,sda,clk,'0','0');
sda <= ((NOT rst)
	OR (EXP28_.EXP)
	OR (EXP29_.EXP)
	OR (NOT main_state_FFd1 AND NOT main_state_FFd2)
	OR (sda AND inner_state_FFd3 AND inner_state_FFd2 AND 
	$OpTx$$OpTx$FX_DC$40_INV$388));
sda <= sda_I when sda_OE = '1' else 'Z';
sda_OE <= link;


seg_data(0) <= '1';


seg_data(1) <= ((EXP13_.EXP)
	OR (NOT en(1) AND NOT readData_reg(1) AND NOT readData_reg(2) AND 
	NOT readData_reg(3))
	OR (en(1) AND writeData_reg(0) AND writeData_reg(1) AND 
	writeData_reg(2) AND NOT writeData_reg(3))
	OR (en(1) AND NOT writeData_reg(0) AND NOT writeData_reg(1) AND 
	writeData_reg(2) AND writeData_reg(3))
	OR (NOT en(1) AND readData_reg(0) AND readData_reg(1) AND 
	readData_reg(2) AND NOT readData_reg(3))
	OR (NOT en(1) AND N