📄 i2c.rpt
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FDCPE_clk_div0: FDCPE port map (clk_div(0),clk_div_D(0),clk,'0','0');
clk_div_D(0) <= (rst AND NOT clk_div(0));
FDCPE_clk_div1: FDCPE port map (clk_div(1),clk_div_D(1),clk,'0','0');
clk_div_D(1) <= ((rst AND clk_div(0) AND NOT clk_div(1))
OR (rst AND NOT clk_div(0) AND clk_div(1)));
FTCPE_clk_div2: FTCPE port map (clk_div(2),clk_div_T(2),clk,'0','0');
clk_div_T(2) <= ((rst AND NOT clk_div(0))
OR (rst AND NOT clk_div(1))
OR (NOT rst AND NOT clk_div(2))
OR (NOT clk_div(2) AND NOT clk_div(3) AND NOT clk_div(4) AND
clk_div(5) AND clk_div(6) AND NOT clk_div(7)));
FTCPE_clk_div3: FTCPE port map (clk_div(3),clk_div_T(3),clk,'0','0');
clk_div_T(3) <= ((NOT rst AND clk_div(3))
OR (rst AND clk_div(0) AND clk_div(1) AND clk_div(2)));
FTCPE_clk_div4: FTCPE port map (clk_div(4),clk_div_T(4),clk,'0','0');
clk_div_T(4) <= ((NOT rst AND clk_div(4))
OR (rst AND clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3)));
FTCPE_clk_div5: FTCPE port map (clk_div(5),clk_div_T(5),clk,'0','0');
clk_div_T(5) <= ((NOT rst AND clk_div(5))
OR (rst AND clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4))
OR (clk_div(0) AND clk_div(1) AND NOT clk_div(2) AND
NOT clk_div(3) AND NOT clk_div(4) AND clk_div(5) AND clk_div(6) AND
NOT clk_div(7)));
FTCPE_clk_div6: FTCPE port map (clk_div(6),clk_div_T(6),clk,'0','0');
clk_div_T(6) <= ((NOT rst AND clk_div(6))
OR (rst AND clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4) AND clk_div(5))
OR (clk_div(0) AND clk_div(1) AND NOT clk_div(2) AND
NOT clk_div(3) AND NOT clk_div(4) AND clk_div(5) AND clk_div(6) AND
NOT clk_div(7)));
FTCPE_clk_div7: FTCPE port map (clk_div(7),clk_div_T(7),clk,'0','0');
clk_div_T(7) <= ((NOT rst AND clk_div(7))
OR (rst AND clk_div(0) AND clk_div(1) AND clk_div(2) AND
clk_div(3) AND clk_div(4) AND clk_div(5) AND clk_div(6)));
FTCPE_cnt_delay0: FTCPE port map (cnt_delay(0),cnt_delay_T(0),clk,'0','0');
cnt_delay_T(0) <= ((rst AND NOT start_delaycnt)
OR (NOT rst AND NOT cnt_delay(0))
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9)));
FTCPE_cnt_delay1: FTCPE port map (cnt_delay(1),cnt_delay_T(1),clk,'0','0');
cnt_delay_T(1) <= ((NOT rst AND cnt_delay(1))
OR (rst AND cnt_delay(0) AND start_delaycnt));
FTCPE_cnt_delay2: FTCPE port map (cnt_delay(2),cnt_delay_T(2),clk,'0','0');
cnt_delay_T(2) <= ((NOT rst AND cnt_delay(2))
OR (rst AND cnt_delay(0) AND cnt_delay(1) AND
start_delaycnt));
FTCPE_cnt_delay3: FTCPE port map (cnt_delay(3),cnt_delay_T(3),clk,'0','0');
cnt_delay_T(3) <= ((NOT rst AND cnt_delay(3))
OR (rst AND cnt_delay(0) AND cnt_delay(1) AND
cnt_delay(2) AND start_delaycnt));
FTCPE_cnt_delay4: FTCPE port map (cnt_delay(4),cnt_delay_T(4),clk,'0','0');
cnt_delay_T(4) <= ((NOT rst AND cnt_delay(4))
OR (rst AND cnt_delay(0) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND start_delaycnt));
FTCPE_cnt_delay5: FTCPE port map (cnt_delay(5),cnt_delay_T(5),clk,'0','0');
cnt_delay_T(5) <= ((NOT rst AND cnt_delay(5))
OR (rst AND cnt_delay(0) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND start_delaycnt));
FTCPE_cnt_delay6: FTCPE port map (cnt_delay(6),cnt_delay_T(6),clk,'0','0');
cnt_delay_T(6) <= ((NOT rst AND cnt_delay(6))
OR (rst AND cnt_delay(0) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
start_delaycnt));
FTCPE_cnt_delay7: FTCPE port map (cnt_delay(7),cnt_delay_T(7),clk,'0','0');
cnt_delay_T(7) <= ((NOT rst AND cnt_delay(7))
OR (rst AND cnt_delay(0) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND start_delaycnt));
FTCPE_cnt_delay8: FTCPE port map (cnt_delay(8),cnt_delay_T(8),clk,'0','0');
cnt_delay_T(8) <= ((NOT rst AND cnt_delay(8))
OR (rst AND cnt_delay(0) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND start_delaycnt)
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay9: FTCPE port map (cnt_delay(9),cnt_delay_T(9),clk,'0','0');
cnt_delay_T(9) <= ((NOT rst AND cnt_delay(9))
OR (rst AND cnt_delay(0) AND cnt_delay(8) AND
cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND
cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND start_delaycnt));
FTCPE_cnt_delay10: FTCPE port map (cnt_delay(10),cnt_delay_T(10),clk,'0','0');
cnt_delay_T(10) <= ((NOT rst AND cnt_delay(10))
OR (rst AND cnt_delay(0) AND cnt_delay(8) AND
cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND
cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9) AND
start_delaycnt)
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay11: FTCPE port map (cnt_delay(11),cnt_delay_T(11),clk,'0','0');
cnt_delay_T(11) <= ((NOT rst AND cnt_delay(11))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(8) AND cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND
cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND
cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay12: FTCPE port map (cnt_delay(12),cnt_delay_T(12),clk,'0','0');
cnt_delay_T(12) <= ((NOT rst AND cnt_delay(12))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(8) AND cnt_delay(11) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND
cnt_delay(7) AND cnt_delay(9) AND start_delaycnt)
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay13: FTCPE port map (cnt_delay(13),cnt_delay_T(13),clk,'0','0');
cnt_delay_T(13) <= ((NOT rst AND cnt_delay(13))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(12) AND cnt_delay(8) AND cnt_delay(11) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9) AND start_delaycnt)
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay14: FTCPE port map (cnt_delay(14),cnt_delay_T(14),clk,'0','0');
cnt_delay_T(14) <= ((NOT rst AND cnt_delay(14))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(12) AND cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND
cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND
cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9) AND
start_delaycnt));
FTCPE_cnt_delay15: FTCPE port map (cnt_delay(15),cnt_delay_T(15),clk,'0','0');
cnt_delay_T(15) <= ((NOT rst AND cnt_delay(15))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(12) AND cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND
cnt_delay(14) AND cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND
cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND
cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay16: FTCPE port map (cnt_delay(16),cnt_delay_T(16),clk,'0','0');
cnt_delay_T(16) <= ((NOT rst AND cnt_delay(16))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(12) AND cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND
cnt_delay(14) AND cnt_delay(15) AND cnt_delay(1) AND cnt_delay(2) AND
cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND
cnt_delay(7) AND cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay17: FTCPE port map (cnt_delay(17),cnt_delay_T(17),clk,'0','0');
cnt_delay_T(17) <= ((NOT rst AND cnt_delay(17))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(12) AND cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND
cnt_delay(14) AND cnt_delay(15) AND cnt_delay(16) AND cnt_delay(1) AND
cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND cnt_delay(5) AND
cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay18: FTCPE port map (cnt_delay(18),cnt_delay_T(18),clk,'0','0');
cnt_delay_T(18) <= ((NOT rst AND cnt_delay(18))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(12) AND cnt_delay(13) AND cnt_delay(8) AND cnt_delay(11) AND
cnt_delay(14) AND cnt_delay(15) AND cnt_delay(16) AND cnt_delay(17) AND
cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND cnt_delay(4) AND
cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND cnt_delay(9) AND
start_delaycnt)
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9) AND start_delaycnt));
FTCPE_cnt_delay19: FTCPE port map (cnt_delay(19),cnt_delay_T(19),clk,'0','0');
cnt_delay_T(19) <= ((NOT rst AND cnt_delay(19))
OR (rst AND cnt_delay(0) AND cnt_delay(10) AND
cnt_delay(12) AND cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND
cnt_delay(11) AND cnt_delay(14) AND cnt_delay(15) AND cnt_delay(16) AND
cnt_delay(17) AND cnt_delay(1) AND cnt_delay(2) AND cnt_delay(3) AND
cnt_delay(4) AND cnt_delay(5) AND cnt_delay(6) AND cnt_delay(7) AND
cnt_delay(9) AND start_delaycnt)
OR (NOT cnt_delay(0) AND cnt_delay(10) AND cnt_delay(12) AND
cnt_delay(13) AND cnt_delay(18) AND cnt_delay(8) AND NOT cnt_delay(11) AND
NOT cnt_delay(14) AND NOT cnt_delay(15) AND NOT cnt_delay(16) AND NOT cnt_delay(17) AND
cnt_delay(19) AND NOT cnt_delay(1) AND NOT cnt_delay(2) AND NOT cnt_delay(3) AND
NOT cnt_delay(4) AND NOT cnt_delay(5) AND NOT cnt_delay(6) AND NOT cnt_delay(7) AND
NOT cnt_delay(9) AND start_delaycnt));
FDCPE_cnt_scan0: FDCPE port map (cnt_scan(0),cnt_scan_D(0),clk,'0','0');
cnt_scan_D(0) <= (rst AND NOT cnt_scan(0));
FDCPE_cnt_scan1: FDCPE port map (cnt_scan(1),cnt_scan_D(1),clk,'0','0');
cnt_scan_D(1) <= ((rst AND cnt_scan(0) AND NOT cnt_scan(1))
OR (rst AND NOT cnt_scan(0) AND cnt_scan(1)));
FTCPE_cnt_scan2: FTCPE port map (cnt_scan(2),cnt_scan_T(2),clk,'0','0');
cnt_scan_T(2) <= ((NOT rst AND cnt_scan(2))
OR (rst AND cnt_scan(0) AND cnt_scan(1)));
FTCPE_cnt_scan3: FTCPE port map (cnt_scan(3),cnt_scan_T(3),clk,'0','0');
cnt_scan_T(3) <= ((NOT rst AND cnt_scan(3))
OR (rst AND cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2)));
FTCPE_cnt_scan4: FTCPE port map (cnt_scan(4),cnt_scan_T(4),clk,'0','0');
cnt_scan_T(4) <= ((NOT rst AND cnt_scan(4))
OR (rst AND cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3)));
FTCPE_cnt_scan5: FTCPE port map (cnt_scan(5),cnt_scan_T(5),clk,'0','0');
cnt_scan_T(5) <= ((NOT rst AND cnt_scan(5))
OR (rst AND cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4)));
FTCPE_cnt_scan6: FTCPE port map (cnt_scan(6),cnt_scan_T(6),clk,'0','0');
cnt_scan_T(6) <= ((NOT rst AND cnt_scan(6))
OR (rst AND cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5)));
FTCPE_cnt_scan7: FTCPE port map (cnt_scan(7),cnt_scan_T(7),clk,'0','0');
cnt_scan_T(7) <= ((NOT rst AND cnt_scan(7))
OR (rst AND cnt_scan(0) AND cnt_scan(1) AND cnt_scan(2) AND
cnt_scan(3) AND cnt_scan(4) AND cnt_scan(5) AND cnt_scan(6)));
FTCPE_cnt_scan8: FTCPE port map (cnt_scan(8),cnt_scan_T(8),clk,'0','0');
cnt_scan_T(8) <= ((NOT rst AND cnt_scan(8))
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