📄 i2c.rpt
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cnt_delay<16> XXXXXXXXX...XXXXXXXXX...........X.X..... 20
cnt_delay<15> XXXXXXXX....XXXXXXXXX...........X.X..... 19
cnt_delay<14> XXXXXXX.....XXXXXXXXX...........X.X..... 18
cnt_delay<11> XXXX........XXXXXXXXX...........X.X..... 15
cnt_delay<8> XXXXXXXXXXXXXXXXXXXXX...........X.X..... 23
cnt_delay<19> XXXXXXXXXXXXXXXXXXXXX...........X.X..... 23
cnt_delay<18> XXXXXXXXXXXXXXXXXXXXX...........X.X..... 23
cnt_delay<13> XXXXXXXXXXXXXXXXXXXXX...........X.X..... 23
cnt_delay<12> XXXXXXXXXXXXXXXXXXXXX...........X.X..... 23
cnt_delay<10> XXXXXXXXXXXXXXXXXXXXX...........X.X..... 23
cnt_delay<0> XXXXXXXXXXXXXXXXXXXXX...........X.X..... 23
start_delaycnt XXXXXXXXXXXXXXXXXXXXX......XX..XX.XX.... 27
main_state_FFd2 XXXXXXXXXXXXXXXXXXXXX.XXXXXXXXX.XX.X.... 33
main_state_FFd1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX.X.... 35
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 25/29
Number of signals used by logic mapping into function block: 25
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
phase3 2 0 0 3 FB2_1 142 I/O (b)
phase2 2 0 0 3 FB2_2 143 GSR/I/O (b)
phase1 2 0 0 3 FB2_3 (b) (b)
phase0 2 0 0 3 FB2_4 4 I/O (b)
clk_div<0> 2 0 0 3 FB2_5 2 GTS/I/O (b)
cnt_delay<5> 3 0 0 2 FB2_6 3 GTS/I/O (b)
cnt_delay<4> 3 0 0 2 FB2_7 (b) (b)
cnt_delay<3> 3 0 0 2 FB2_8 5 GTS/I/O (b)
cnt_delay<2> 3 0 0 2 FB2_9 6 GTS/I/O (b)
cnt_delay<1> 3 0 0 2 FB2_10 7 I/O (b)
clk_div<7> 3 0 0 2 FB2_11 9 I/O (b)
clk_div<4> 3 0 0 2 FB2_12 10 I/O (b)
clk_div<3> 3 0 0 2 FB2_13 12 I/O (b)
clk_div<1> 3 0 0 2 FB2_14 11 I/O (b)
writeData_reg<0> 4 0 0 1 FB2_15 13 I/O (b)
clk_div<6> 4 0 0 1 FB2_16 14 I/O (b)
clk_div<5> 4 0 0 1 FB2_17 15 I/O (b)
clk_div<2> 5 0 0 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 10: cnt_delay<0> 18: main_state_FFd2
2: clk_div<0> 11: cnt_delay<1> 19: phase0
3: clk_div<1> 12: cnt_delay<2> 20: phase1
4: clk_div<2> 13: cnt_delay<3> 21: phase2
5: clk_div<3> 14: cnt_delay<4> 22: phase3
6: clk_div<4> 15: cnt_delay<5> 23: rst
7: clk_div<5> 16: data_in<0> 24: start_delaycnt
8: clk_div<6> 17: main_state_FFd1 25: writeData_reg<0>
9: clk_div<7>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
phase3 XXXXXXXXX............XX................. 11
phase2 XXXXXXXXX...........X.X................. 11
phase1 XXXXXXXXX..........X..X................. 11
phase0 XXXXXXXXX.........X...X................. 11
clk_div<0> XX....................X................. 3
cnt_delay<5> X........XXXXXX.......XX................ 9
cnt_delay<4> X........XXXXX........XX................ 8
cnt_delay<3> X........XXXX.........XX................ 7
cnt_delay<2> X........XXX..........XX................ 6
cnt_delay<1> X........XX...........XX................ 5
clk_div<7> XXXXXXXXX.............X................. 10
clk_div<4> XXXXXX................X................. 7
clk_div<3> XXXXX.................X................. 6
clk_div<1> XXX...................X................. 4
writeData_reg<0> X..............XXX....X.X............... 6
clk_div<6> XXXXXXXXX.............X................. 10
clk_div<5> XXXXXXXXX.............X................. 10
clk_div<2> XXXXXXXXX.............X................. 10
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 26/28
Number of signals used by logic mapping into function block: 26
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
$OpTx$$OpTx$FX_DC$53_INV$390
1 0 0 4 FB3_1 39 I/O (b)
$OpTx$$OpTx$FX_DC$44_INV$389
1 0 0 4 FB3_2 32 GCK/I/O (b)
$OpTx$$OpTx$FX_DC$40_INV$388
1 0 0 4 FB3_3 41 I/O (b)
$OpTx$$OpTx$FX_DC$38_INV$387
1 0 0 4 FB3_4 44 I/O (b)
cnt_scan<0> 2 0 0 3 FB3_5 33 I/O (b)
$OpTx$FX_DC$59 2 0 0 3 FB3_6 34 I/O (b)
$OpTx$FX_DC$48 2 0 0 3 FB3_7 46 I/O (b)
$OpTx$FX_DC$41 2 0 0 3 FB3_8 38 GCK/I/O (b)
$OpTx$$OpTx$FX_DC$69_INV$394
2 0 0 3 FB3_9 40 I/O (b)
$OpTx$$OpTx$FX_DC$63_INV$393
2 0 0 3 FB3_10 48 I/O (b)
cnt_scan<3> 3 0 0 2 FB3_11 43 I/O (b)
cnt_scan<2> 3 0 0 2 FB3_12 45 I/O (b)
cnt_scan<1> 3 0 0 2 FB3_13 (b) (b)
$OpTx$FX_DC$67 3 0 0 2 FB3_14 49 I/O (b)
$OpTx$FX_DC$60 3 0 0 2 FB3_15 50 I/O (b)
writeData_reg<3> 4 0 0 1 FB3_16 (b) (b)
writeData_reg<2> 4 0 0 1 FB3_17 51 I/O (b)
writeData_reg<1> 4 0 0 1 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: sda.PIN 10: i2c_state_FFd1 19: main_state_FFd2
2: clk 11: i2c_state_FFd2 20: phase0
3: cnt_scan<0> 12: i2c_state_FFd3 21: phase3
4: cnt_scan<1> 13: inner_state_FFd1 22: rst
5: cnt_scan<2> 14: inner_state_FFd2 23: sda
6: cnt_scan<3> 15: inner_state_FFd3 24: writeData_reg<1>
7: data_in<1> 16: inner_state_FFd4 25: writeData_reg<2>
8: data_in<2> 17: link 26: writeData_reg<3>
9: data_in<3> 18: main_state_FFd1
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
$OpTx$$OpTx$FX_DC$53_INV$390
............XX.......................... 2
$OpTx$$OpTx$FX_DC$44_INV$389
..........X......X...................... 2
$OpTx$$OpTx$FX_DC$40_INV$388
............X..X........................ 2
$OpTx$$OpTx$FX_DC$38_INV$387
.........XX............................. 2
cnt_scan<0> .XX..................X.................. 3
$OpTx$FX_DC$59 ..............XXX....................... 3
$OpTx$FX_DC$48 ..........X.......X......X.............. 3
$OpTx$FX_DC$41 .........XX......X...................... 3
$OpTx$$OpTx$FX_DC$69_INV$394
............XXXX........................ 4
$OpTx$$OpTx$FX_DC$63_INV$393
...........XX.XX........................ 4
cnt_scan<3> .XXXXX...............X.................. 6
cnt_scan<2> .XXXX................X.................. 5
cnt_scan<1> .XXX.................X.................. 4
$OpTx$FX_DC$67 X..........XX.XX...X..X................. 7
$OpTx$FX_DC$60 .........XXX.....XX.X................... 6
writeData_reg<3> .X......X........XX..X...X.............. 6
writeData_reg<2> .X.....X.........XX..X..X............... 6
writeData_reg<1> .X....X..........XX..X.X................ 6
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 28/26
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
seg_data<1> 12 7<- 0 0 FB4_1 118 I/O O
(unused) 0 0 /\5 0 FB4_2 126 I/O (b)
cnt_scan<8> 3 0 /\2 0 FB4_3 133 I/O (b)
cnt_scan<7> 3 0 0 2 FB4_4 (b) (b)
cnt_scan<6> 3 0 0 2 FB4_5 128 I/O I
cnt_scan<5> 3 0 0 2 FB4_6 129 I/O (b)
cnt_scan<4> 3 0 0 2 FB4_7 (b) (b)
cnt_scan<11> 3 0 0 2 FB4_8 130 I/O (b)
en<1> 3 0 0 2 FB4_9 131 I/O O
cnt_scan<10> 3 0 \/2 0 FB4_10 135 I/O (b)
en<0> 3 2<- \/4 0 FB4_11 132 I/O O
(unused) 0 0 \/5 0 FB4_12 134 I/O (b)
seg_data<7>_BUFR 12 9<- \/2 0 FB4_13 137 I/O (b)
seg_data<4>_BUFR 12 7<- 0 0 FB4_14 136 I/O (b)
(unused) 0 0 /\5 0 FB4_15 138 I/O (b)
(unused) 0 0 \/5 0 FB4_16 139 I/O (b)
seg_data<2>_BUFR 12 7<- 0 0 FB4_17 140 I/O (b)
cnt_scan<9> 3 0 /\2 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 11: cnt_scan<7> 20: readData_reg<4>
2: cnt_scan<0> 12: cnt_scan<8> 21: readData_reg<5>
3: cnt_scan<10> 13: cnt_scan<9> 22: readData_reg<6>
4: cnt_scan<11> 14: en<0> 23: readData_reg<7>
5: cnt_scan<1> 15: en<1> 24: rst
6: cnt_scan<2> 16: readData_reg<0> 25: writeData_reg<0>
7: cnt_scan<3> 17: readData_reg<1> 26: writeData_reg<1>
8: cnt_scan<4> 18: readData_reg<2> 27: writeData_reg<2>
9: cnt_scan<5> 19: readData_reg<3> 28: writeData_reg<3>
10: cnt_scan<6>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
seg_data<1> .............XXXXXXXXXX.XXXX............ 14
cnt_scan<8> XX..XXXXXXXX...........X................ 11
cnt_scan<7> XX..XXXXXXX............X................ 10
cnt_scan<6> XX..XXXXXX.............X................ 9
cnt_scan<5> XX..XXXXX..............X................ 8
cnt_scan<4> XX..XXXX...............X................ 7
cnt_scan<11> XXXXXXXXXXXXX..........X................ 14
en<1> XXXXXXXXXXXXX.X........X................ 15
cnt_scan<10> XXX.XXXXXXXXX..........X................ 13
en<0> XXXXXXXXXXXXXX.........X................ 15
seg_data<7>_BUFR .............XXXXXXXXXX.XXXX............ 14
seg_data<4>_BUFR .............XXXXXXXXXX.XXXX............ 14
seg_data<2>_BUFR .............XXXXXXXXXX.XXXX............ 14
cnt_scan<9> XX..XXXXXXXXX..........X................ 12
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 2/52
Number of signals used by logic mapping into function block: 2
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 52 I/O
(unused) 0 0 0 5 FB5_3 59 I/O
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 53 I/O
(unused) 0 0 0 5 FB5_6 54 I/O
(unused) 0 0 0 5 FB5_7 66 I/O I
(unused) 0 0 0 5 FB5_8 56 I/O
(unused) 0 0 0 5 FB5_9 57 I/O
(unused) 0 0 0 5 FB5_10 68 I/O
(unused) 0 0 0 5 FB5_11 58 I/O
(unused) 0 0 0 5 FB5_12 60 I/O
(unused) 0 0 0 5 FB5_13 70 I/O
(unused) 0 0 0 5 FB5_14 61 I/O I
(unused) 0 0 0 5 FB5_15 64 I/O I
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 69 I/O I
$OpTx$$OpTx$FX_DC$54_INV$391
1 0 0 4 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: phase1 2: sda
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
$OpTx$$OpTx$FX_DC$54_INV$391
XX...................................... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 30/24
Number of signals used by logic mapping into function block: 30
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
inner_state_FFd3 14 9<- 0 0 FB6_1 (b) (b)
seg_data<7> 1 0 /\4 0 FB6_2 106 I/O O
(unused) 0 0 \/5 0 FB6_3 (b) (b)
seg_data<5> 10 5<- 0 0 FB6_4 111 I/O O
(unused) 0 0 \/5 0 FB6_5 110 I/O (b)
readData_reg<2> 11 6<- 0 0 FB6_6 112 I/O (b)
$OpTx$FX_DC$70 4 0 /\1 0 FB6_7 (b) (b)
seg_data<4> 1 0 \/1 3 FB6_8 113 I/O O
seg_data<2> 1 1<- \/5 0 FB6_9 116 I/O O
seg_data<3> 10 5<- 0 0 FB6_10 115 I/O O
seg_data<0> 0 0 \/3 2 FB6_11 119 I/O O
(unused) 0 0 \/5 0 FB6_12 120 I/O (b)
readData_reg<1> 11 8<- \/2 0 FB6_13 (b) (b)
(unused) 0 0 \/5 0 FB6_14 121 I/O (b)
inner_state_FFd2 11 7<- \/1 0 FB6_15 124 I/O (b)
inner_state_FFd1 11 6<- 0 0 FB6_16 117 I/O (b)
(unused) 0 0 /\5 0 FB6_17 125 I/O (b)
(unused) 0 0 \/5 0 FB6_18 (b) (b)
Signals Used by Logic in Function Block
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