i2c.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Counters                         : 3
 12-bit up counter                 : 1
 20-bit up counter                 : 1
 8-bit up counter                  : 1
# Registers                        : 27
 1-bit register                    : 25
 2-bit register                    : 1
 8-bit register                    : 1
# Multiplexers                     : 2
 1-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 1-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <writeData_reg_7> (without init value) has a constant value of 0 in block <i2c>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <writeData_reg_6> (without init value) has a constant value of 0 in block <i2c>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <writeData_reg_4> (without init value) has a constant value of 0 in block <i2c>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <writeData_reg_5> (without init value) has a constant value of 0 in block <i2c>.

Optimizing unit <i2c> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c, actual ratio is 17.
FlipFlop i2c_state_FFd1 has been replicated 3 time(s)
FlipFlop i2c_state_FFd2 has been replicated 3 time(s)
FlipFlop i2c_state_FFd3 has been replicated 3 time(s)
FlipFlop inner_state_FFd1 has been replicated 3 time(s)
FlipFlop inner_state_FFd3 has been replicated 2 time(s)
FlipFlop inner_state_FFd4 has been replicated 3 time(s)
FlipFlop main_state_FFd1 has been replicated 3 time(s)
FlipFlop main_state_FFd2 has been replicated 3 time(s)
FlipFlop phase3 has been replicated 3 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : i2c.ngr
Top Level Output File Name         : i2c
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 21

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 23
#      1-bit register              : 20
#      12-bit register             : 3
# Multiplexers                     : 2
#      1-bit 4-to-1 multiplexer    : 1
#      8-bit 4-to-1 multiplexer    : 1
# Tristates                        : 1
#      1-bit tristate buffer       : 1
# Adders/Subtractors               : 3
#      12-bit adder                : 3

Cell Usage :
# BELS                             : 325
#      GND                         : 1
#      INV                         : 7
#      LUT1                        : 37
#      LUT2                        : 18
#      LUT2_D                      : 7
#      LUT2_L                      : 4
#      LUT3                        : 16
#      LUT3_D                      : 5
#      LUT3_L                      : 7
#      LUT4                        : 83
#      LUT4_D                      : 10
#      LUT4_L                      : 47
#      MUXCY                       : 37
#      MUXF5                       : 8
#      VCC                         : 1
#      XORCY                       : 37
# FlipFlops/Latches                : 97
#      FDR                         : 29
#      FDRE                        : 39
#      FDRS                        : 24
#      FDS                         : 2
#      FDSE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 20
#      IBUF                        : 7
#      IOBUF                       : 1
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     127  out of    768    16%  
 Number of Slice Flip Flops:            97  out of   1536     6%  
 Number of 4 input LUTs:               234  out of   1536    15%  
 Number of bonded IOBs:                 21  out of     96    21%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 97    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 10.505ns (Maximum Frequency: 95.193MHz)
   Minimum input arrival time before clock: 8.938ns
   Maximum output required time after clock: 13.475ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 10.505ns (frequency: 95.193MHz)
  Total number of paths / destination ports: 2363 / 187
-------------------------------------------------------------------------
Delay:               10.505ns (Levels of Logic = 5)
  Source:            inner_state_FFd3 (FF)
  Destination:       sda_buf (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: inner_state_FFd3 to sda_buf
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q            25   1.085   3.105  inner_state_FFd3 (inner_state_FFd3)
     LUT3_L:I1->LO         1   0.549   0.000  _n0034253_SW1_G (N1151)
     MUXF5:I1->O           1   0.305   1.035  _n0034253_SW1 (N1080)
     LUT4:I2->O            1   0.549   1.035  _n0034281 (CHOICE2588)
     LUT4:I1->O            1   0.549   1.035  _n0034421 (CHOICE2617)
     LUT4_L:I3->LO         1   0.549   0.000  _n0034516 (_n0034)
     FDS:D                     0.709          sda_buf
    ----------------------------------------
    Total                     10.505ns (4.295ns logic, 6.210ns route)
                                       (40.9% logic, 59.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 122 / 113
-------------------------------------------------------------------------
Offset:              8.938ns (Levels of Logic = 6)
  Source:            sda (PAD)
  Destination:       sda_buf (FF)
  Destination Clock: clk rising

  Data Path: sda to sda_buf
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           2   0.776   1.206  sda_IOBUF (N1059)
     LUT3_D:I2->O          3   0.549   1.332  _n00531 (_n0053)
     LUT4:I0->O            1   0.549   1.035  _n003426 (CHOICE2531)
     LUT4:I3->O            1   0.549   1.035  _n003478 (CHOICE2545)
     LUT4_L:I3->LO         1   0.549   0.100  _n0034193 (CHOICE2569)
     LUT4_L:I2->LO         1   0.549   0.000  _n0034516 (_n0034)
     FDS:D                     0.709          sda_buf
    ----------------------------------------
    Total                      8.938ns (4.230ns logic, 4.708ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 159 / 11
-------------------------------------------------------------------------
Offset:              13.475ns (Levels of Logic = 4)
  Source:            en_0 (FF)
  Destination:       seg_data<7> (PAD)
  Source Clock:      clk rising

  Data Path: en_0 to seg_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            13   1.085   2.250  en_0 (en_0)
     LUT4:I0->O            7   0.549   1.755  seg_data_buf<3>1 (seg_data_buf<3>)
     LUT4:I3->O            1   0.549   1.035  Mrom__n0047_inst_lut4_71 (_n0047<7>)
     LUT4:I3->O            1   0.549   1.035  seg_data<7>2 (seg_data_7_OBUF)
     OBUF:I->O                 4.668          seg_data_7_OBUF (seg_data<7>)
    ----------------------------------------
    Total                     13.475ns (7.400ns logic, 6.075ns route)
                                       (54.9% logic, 45.1% route)

=========================================================================
CPU : 16.37 / 19.55 s | Elapsed : 16.00 / 19.00 s
 
--> 

Total memory usage is 80292 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    1 (   0 filtered)