i2c.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 3.10 s | Elapsed : 0.00 / 3.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 3.10 s | Elapsed : 0.00 / 3.00 s
 
--> Reading design: i2c.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "i2c.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "i2c"
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : i2c
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : i2c.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "i2c.v"
Module <i2c> compiled
No errors in compilation
Analysis of file <"i2c.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <i2c>.
	div_parameter = 100
	start = <u>0000
	first = <u>0001
	second = <u>0010
	third = <u>0011
	fourth = <u>0100
	fifth = <u>0101
	sixth = <u>0110
	seventh = <u>0111
	eighth = <u>1000
	ack = <u>1001
	stop = <u>1010
	ini = <u>000
	sendaddr = <u>001
	write_data = <u>010
	read_data = <u>011
	read_ini = <u>000100
Module <i2c> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <addr> in unit <i2c> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <i2c>.
    Related source file is "i2c.v".
    Found finite state machine <FSM_0> for signal <main_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 38                                             |
    | Inputs             | 14                                             |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <i2c_state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 30                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <inner_state>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 184                                            |
    | Inputs             | 11                                             |
    | Outputs            | 11                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x8-bit ROM for signal <$n0047>.
    Found 2-bit register for signal <en>.
    Found 1-bit tristate buffer for signal <sda>.
    Found 1-bit register for signal <scl>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0050>.
    Found 8-bit up counter for signal <clk_div>.
    Found 20-bit up counter for signal <cnt_delay>.
    Found 12-bit up counter for signal <cnt_scan>.
    Found 1-bit register for signal <link>.
    Found 1-bit register for signal <phase0>.
    Found 1-bit register for signal <phase1>.
    Found 1-bit register for signal <phase2>.
    Found 1-bit register for signal <phase3>.
    Found 8-bit register for signal <readData_reg>.
    Found 1-bit register for signal <sda_buf>.
    Found 8-bit 4-to-1 multiplexer for signal <seg_data_buf>.
    Found 1-bit register for signal <start_delaycnt>.
    Found 8-bit register for signal <writeData_reg>.
    Summary:
	inferred   3 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   3 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
	inferred   1 Tristate(s).
Unit <i2c> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <FSM_2> on signal <inner_state[1:4]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0001  | 0001
 0010  | 0010
 0011  | 0011
 0100  | 0100
 0101  | 0101
 0110  | 0110
 0111  | 0111
 1000  | 1000
 1001  | 1001
 1010  | 1010
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <i2c_state[1:3]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 100
 100   | 011
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <main_state[1:2]> with sequential encoding.
-------------------