📄 vga_vl.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: vga_vl Date: 2-21-2006, 3:56PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
32 /144 ( 22%) 243 /720 ( 34%) 138/432 ( 32%) 25 /144 ( 17%) 9 /117 ( 8%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 1/18 13/54 9/90 0/15
FB2 2/18 13/54 14/90 1/15
FB3 1/18 21/54 13/90 1/15
FB4 7/18 28/54 69/90 4/15
FB5 11/18 14/54 49/90 0/14
FB6 2/18 13/54 15/90 0/13
FB7 7/18 13/54 49/90 0/15
FB8 1/18 23/54 25/90 0/15
----- ----- ----- -----
32/144 138/432 243/720 6/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 3 3 | I/O : 9 109
Output : 6 6 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 9 9
** Power Data **
There are 32 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB4,
because too many function block product terms are required. Buffering output
signal pixel<1> to allow all signals assigned to this function block to be
placed.
************************* Summary of Mapped Logic ************************
** 6 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
vsync 5 13 FB2_1 142 I/O O STD FAST RESET
blank 13 21 FB3_17 51 I/O O STD FAST RESET
pixel<0> 25 21 FB4_10 135 I/O O STD FAST
pixel<1> 1 1 FB4_13 137 I/O O STD FAST
pixel<2> 18 22 FB4_15 138 I/O O STD FAST
hsync 4 11 FB4_16 139 I/O O STD FAST RESET
** 26 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
vcnt<1> 9 13 FB1_18 STD RESET
vcnt<4> 9 13 FB2_18 STD RESET
hcnt<1> 6 10 FB4_1 STD RESET
$OpTx$DEC_hsyncint$0 6 10 FB4_2 STD
hcnt<3> 9 12 FB4_3 STD RESET
hcnt<4> 9 13 FB5_1 STD RESET
$OpTx$$OpTx$FX_DC$30_INV$386 1 2 FB5_8 STD
$OpTx$DEC_hsyncint$1 2 9 FB5_9 STD
hcnt<9> 4 13 FB5_10 STD RESET
hcnt<8> 4 12 FB5_11 STD RESET
hcnt<7> 4 11 FB5_12 STD RESET
hcnt<6> 4 10 FB5_13 STD RESET
hcnt<10> 4 13 FB5_14 STD RESET
hcnt<0> 4 9 FB5_15 STD RESET
hcnt<5> 5 13 FB5_16 STD RESET
hcnt<2> 8 11 FB5_18 STD RESET
vcnt<3> 10 13 FB6_1 STD RESET
vcnt<8> 5 13 FB6_17 STD RESET
vcnt<9> 7 13 FB7_2 STD RESET
vcnt<0> 7 12 FB7_3 STD RESET
vcnt<6> 9 13 FB7_5 STD RESET
vcnt<5> 9 13 FB7_7 STD RESET
vcnt<2> 10 13 FB7_8 STD RESET
vcnt<10> 2 2 FB7_9 STD RESET
vcnt<7> 5 12 FB7_18 STD RESET
pixel<1>_BUFR 25 23 FB8_16 STD
** 3 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clock FB4_5 128 I/O I
orient FB5_17 69 I/O I
resetn FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 13/41
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
(unused) 0 0 0 5 FB1_3 17 I/O
(unused) 0 0 0 5 FB1_4 25 I/O
(unused) 0 0 0 5 FB1_5 19 I/O
(unused) 0 0 0 5 FB1_6 20 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 21 I/O
(unused) 0 0 0 5 FB1_9 22 I/O
(unused) 0 0 0 5 FB1_10 31 I/O
(unused) 0 0 0 5 FB1_11 24 I/O
(unused) 0 0 0 5 FB1_12 26 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 27 I/O
(unused) 0 0 0 5 FB1_15 28 I/O
(unused) 0 0 0 5 FB1_16 35 I/O
(unused) 0 0 \/4 1 FB1_17 30 GCK/I/O (b)
vcnt<1> 9 4<- 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: hsync 6: vcnt<2> 10: vcnt<6>
2: resetn 7: vcnt<3> 11: vcnt<7>
3: vcnt<0> 8: vcnt<4> 12: vcnt<8>
4: vcnt<10> 9: vcnt<5> 13: vcnt<9>
5: vcnt<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
vcnt<1> XXXXXXXXXXXXX........................... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 13/41
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
vsync 5 0 0 0 FB2_1 142 I/O O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 0 5 FB2_13 12 I/O
(unused) 0 0 0 5 FB2_14 11 I/O
(unused) 0 0 0 5 FB2_15 13 I/O
(unused) 0 0 0 5 FB2_16 14 I/O
(unused) 0 0 \/4 1 FB2_17 15 I/O (b)
vcnt<4> 9 4<- 0 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: hsync 6: vcnt<2> 10: vcnt<6>
2: resetn 7: vcnt<3> 11: vcnt<7>
3: vcnt<0> 8: vcnt<4> 12: vcnt<8>
4: vcnt<10> 9: vcnt<5> 13: vcnt<9>
5: vcnt<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
vsync XXXXXXXXXXXXX........................... 13
vcnt<4> XXXXXXXXXXXXX........................... 13
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 21/33
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
(unused) 0 0 0 5 FB3_5 33 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
(unused) 0 0 0 5 FB3_9 40 I/O
(unused) 0 0 0 5 FB3_10 48 I/O
(unused) 0 0 0 5 FB3_11 43 I/O
(unused) 0 0 0 5 FB3_12 45 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 49 I/O
(unused) 0 0 0 5 FB3_15 50 I/O
(unused) 0 0 \/4 1 FB3_16 (b) (b)
blank 13 8<- 0 0 FB3_17 51 I/O O
(unused) 0 0 /\4 1 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: clock 8: hcnt<6> 15: vcnt<3>
2: hcnt<10> 9: hcnt<7> 16: vcnt<4>
3: hcnt<1> 10: hcnt<8> 17: vcnt<5>
4: hcnt<2> 11: hcnt<9> 18: vcnt<6>
5: hcnt<3> 12: resetn 19: vcnt<7>
6: hcnt<4> 13: vcnt<10> 20: vcnt<8>
7: hcnt<5> 14: vcnt<2> 21: vcnt<9>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
blank XXXXXXXXXXXXXXXXXXXXX................... 21
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 28/26
Number of signals used by logic mapping into function block: 28
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
hcnt<1> 6 2<- \/1 0 FB4_1 118 I/O (b)
$OpTx$DEC_hsyncint$0
6 1<- 0 0 FB4_2 126 I/O (b)
hcnt<3> 9 4<- 0 0 FB4_3 133 I/O (b)
(unused) 0 0 /\4 1 FB4_4 (b) (b)
(unused) 0 0 0 5 FB4_5 128 I/O I
(unused) 0 0 0 5 FB4_6 129 I/O
(unused) 0 0 \/5 0 FB4_7 (b) (b)
(unused) 0 0 \/5 0 FB4_8 130 I/O (b)
(unused) 0 0 \/5 0 FB4_9 131 I/O (b)
pixel<0> 25 20<- 0 0 FB4_10 135 I/O O
(unused) 0 0 /\5 0 FB4_11 132 I/O (b)
(unused) 0 0 \/1 4 FB4_12 134 I/O (b)
pixel<1> 1 1<- \/5 0 FB4_13 137 I/O O
(unused) 0 0 \/5 0 FB4_14 136 I/O (b)
pixel<2> 18 13<- 0 0 FB4_15 138 I/O O
hsync 4 2<- /\3 0 FB4_16 139 I/O O
(unused) 0 0 /\2 3 FB4_17 140 I/O (b)
(unused) 0 0 \/2 3 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$DEC_hsyncint$1 11: hcnt<6> 20: vcnt<1>
2: blank 12: hcnt<7> 21: vcnt<2>
3: clock 13: hcnt<8> 22: vcnt<3>
4: hcnt<0> 14: hcnt<9> 23: vcnt<4>
5: hcnt<10> 15: orient 24: vcnt<5>
6: hcnt<1> 16: pixel<1>_BUFR 25: vcnt<6>
7: hcnt<2> 17: resetn 26: vcnt<7>
8: hcnt<3> 18: vcnt<0> 27: vcnt<8>
9: hcnt<4> 19: vcnt<10> 28: vcnt<9>
10: hcnt<5>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
hcnt<1> ..XXXX...XXXXX..X....................... 10
$OpTx$DEC_hsyncint$0
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