vga.gfl

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

# Assign Package Pins (Design Module)
if
 $IsCopy 

            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule"
         
# XST (Creating Lso File) : 
vga_vl.lso
# xst flow : RunXST
vga_vl.syr
vga_vl.prj
vga_vl.sprj
vga_vl.ana
vga_vl.stx
vga_vl.cmd_log
vga_vl.ngc
vga_vl.ngr
# Implmentation : Translate (CPLD flow)
__projnav/vga_vl_edfTOngd_tcl.rsp
vga_vl.ngd
vga_vl.bld
vga_vl_ngdbuild.nav
_ngo/netlist.lst
vga_vl.ucf.untf
vga_vl_html
vga_vl.cmd_log
# Implmentation : Fit
__projnav/vga_vl_ngdTOvm6_tcl.rsp
vga_vl.vm6
vga_vl.cxt
vga_vl.blx
vga_vl.mfd
vga_vl.rpt
vga_vl.log
vga_vl.pnx
vga_vl.gyd
vga_vl.xml
vga_vl_build.xml
VGA.ptf
vga_vl.bl
errors.xml
tmperr.err
vga_vl.cmd_log
# Generate Programming File (CPLD flow)
__projnav/vga_vl_vm6TOjed_tcl.rsp
vga_vl.jed
vga_vl.isc
vga_vl.cmd_log
# Implmentation : Generate Timing
__projnav/vga_vl_vm6TOtim_tcl.rsp
vga_vl.tim
vga_vl.mod
vga_vl.data
vga_vl.cmd_log
e:\temp\95144\veriloge\vga/vga_vl_html
__projnav\taengine.err
# Implmentation : FitRpt
vga_vl_html
vga_vl._hrpt
vga_vl.cmd_log
# Implmentation : FitRpt
vga_vl.imp
# Configure Device (iMPACT)
vga_vl.prm
vga_vl.isc
vga_vl.svf
xilinx.sys
vga_vl.mcs
vga_vl.exo
vga_vl.hex
vga_vl.tek
vga_vl.dst
vga_vl.dst_compressed
vga_vl.mpm
_impact.cmd
_impact.log
# XST (Creating Lso File) : 
vga_vl.lso
# xst flow : RunXST
vga_vl_summary.html
# xst flow : RunXST
vga_vl.syr
vga_vl.prj
vga_vl.sprj
vga_vl.ana
vga_vl.stx
vga_vl.cmd_log
vga_vl.ngc
vga_vl.ngr
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"e:\temp\spartan2\veriloge\interface\vga/_ngo"
vga_vl.ngd
vga_vl_ngdbuild.nav
vga_vl.bld
vga_vl.ucf.untf
vga_vl.cmd_log
# Implementation : Map
vga_vl_summary.html
# Implementation : Map
vga_vl_map.ncd
vga_vl.ngm
vga_vl.pcf
vga_vl.nc1
vga_vl.mrp
vga_vl_map.mrp
vga_vl.mdf
vga_vl.cmd_log
MAP_NO_GUIDE_FILE_CPF "vga_vl"
vga_vl_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
vga_vl.twr
vga_vl.twx
vga_vl.tsi
vga_vl.cmd_log
# Implementation : Place & Route
vga_vl_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
vga_vl.ncd
vga_vl.par
vga_vl.pad
vga_vl_pad.txt
vga_vl_pad.csv
vga_vl.pad_txt
vga_vl.dly
reportgen.log
vga_vl.xpi
vga_vl.grf
vga_vl.itr
vga_vl_last_par.ncd
vga_vl.placed_ncd_tracker
vga_vl.routed_ncd_tracker
vga_vl.cmd_log
PAR_NO_GUIDE_FILE_CPF "vga_vl"
# Generate Programming File
__projnav/vga_vl_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
vga_vl.ut
# Generate Programming File
vga_vl.bgn
vga_vl.rbt
vga_vl.ll
vga_vl.msk
vga_vl.drc
vga_vl.nky
vga_vl.bit
vga_vl.bin
vga_vl.isc
vga_vl.cmd_log
# Configure Device (iMPACT)
vga_vl.prm
vga_vl.isc
vga_vl.svf
xilinx.sys
vga_vl.mcs
vga_vl.exo
vga_vl.hex
vga_vl.tek
vga_vl.dst
vga_vl.dst_compressed
vga_vl.mpm
_impact.cmd
_impact.log
# xst flow : RunXST
vga_vl_summary.html
# Implmentation : Translate
__projnav/ednTOngd_tcl.rsp
"e:\temp\spartan2\veriloge\interface\vga/_ngo"
vga_vl.ngd
vga_vl_ngdbuild.nav
vga_vl.bld
vga_vl.ucf.untf
vga_vl.cmd_log
# Implementation : Map
vga_vl_summary.html
# Implementation : Map
vga_vl_map.ncd
vga_vl.ngm
vga_vl.pcf
vga_vl.nc1
vga_vl.mrp
vga_vl_map.mrp
vga_vl.mdf
vga_vl.cmd_log
MAP_NO_GUIDE_FILE_CPF "vga_vl"
vga_vl_map.ngm
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
vga_vl.twr
vga_vl.twx
vga_vl.tsi
vga_vl.cmd_log
# Implementation : Place & Route
vga_vl_summary.html
# Implmentation : Place & Route
__projnav/nc1TOncd_tcl.rsp
vga_vl.ncd
vga_vl.par
vga_vl.pad
vga_vl_pad.txt
vga_vl_pad.csv
vga_vl.pad_txt
vga_vl.dly
reportgen.log
vga_vl.xpi
vga_vl.grf
vga_vl.itr
vga_vl_last_par.ncd
vga_vl.placed_ncd_tracker
vga_vl.routed_ncd_tracker
vga_vl.cmd_log
PAR_NO_GUIDE_FILE_CPF "vga_vl"
# Generate Programming File
__projnav/vga_vl_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
vga_vl.ut
# Generate Programming File
vga_vl.bgn
vga_vl.rbt
vga_vl.ll
vga_vl.msk
vga_vl.drc
vga_vl.nky
vga_vl.bit
vga_vl.bin
vga_vl.isc
vga_vl.cmd_log