📄 vga_vl.twr
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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
D:/Xilinx/bin/nt/trce.exe -ise e:\temp\spartan2\veriloge\interface\vga\VGA.ise
-intstyle ise -e 3 -l 3 -s 6 -xml vga_vl vga_vl.ncd -o vga_vl.twr vga_vl.pcf
Design file: vga_vl.ncd
Physical constraint file: vga_vl.pcf
Device,speed: xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clock to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
blank | 9.686(R)|clock_BUFGP | 0.000|
hsync | 10.283(R)|clock_BUFGP | 0.000|
pixel<0> | 18.676(R)|clock_BUFGP | 0.000|
pixel<1> | 18.743(R)|clock_BUFGP | 0.000|
pixel<2> | 18.692(R)|clock_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock | 7.296| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
orient |pixel<0> | 11.163|
orient |pixel<1> | 11.002|
orient |pixel<2> | 14.831|
---------------+---------------+---------+
Analysis completed Tue Mar 14 15:41:33 2006
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Peak Memory Usage: 63 MB
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