vga_vl.cmd_log

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

xst -intstyle ise -ifn __projnav/vga_vl.xst -ofn vga_vl.syr
ngdbuild -dd _ngo -uc vga_vl.ucf -p xc9500xl vga_vl.ngc vga_vl.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt verilog -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper vga_vl.ngd
hprep6 -s IEEE1149 -n vga_vl -i vga_vl
taengine -f vga_vl -w --format html1 -l e:\temp\95144\veriloge\vga/vga_vl_html/tim/timing_report.htm
XSLTProcess "vga_vl_build.xml"
xst -intstyle ise -ifn __projnav/vga_vl.xst -ofn vga_vl.syr
ngdbuild -intstyle ise -dd "e:\temp\spartan2\veriloge\interface\vga/_ngo" -nt timestamp -uc vga_vl.ucf  -p xc2s50-TQ144-6 vga_vl.ngc vga_vl.ngd
map -intstyle ise -p xc2s50-TQ144-6 -cm area -pr b -k 4 -c 100 -tx off -o vga_vl_map.ncd vga_vl.ngd vga_vl.pcf
par -w -intstyle ise -ol std -t 1 vga_vl_map.ncd vga_vl.ncd vga_vl.pcf
trce -intstyle ise -e 3 -l 3 -s 6 -xml vga_vl vga_vl.ncd -o vga_vl.twr vga_vl.pcf
bitgen -intstyle ise -f vga_vl.ut vga_vl.ncd
ngdbuild -intstyle ise -dd "e:\temp\spartan2\veriloge\interface\vga/_ngo" -uc vga_vl.ucf  -p xc2s50-tq144-6 vga_vl.ngc vga_vl.ngd
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o vga_vl_map.ncd vga_vl.ngd vga_vl.pcf
par -w -intstyle ise -ol std -t 1 vga_vl_map.ncd vga_vl.ncd vga_vl.pcf
trce -intstyle ise -e 3 -l 3 -s 6 -xml vga_vl vga_vl.ncd -o vga_vl.twr vga_vl.pcf
bitgen -intstyle ise -f vga_vl.ut vga_vl.ncd