vga_vl.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

#      1-bit register              : 3
#      11-bit register             : 2
# Adders/Subtractors               : 2
#      11-bit adder                : 2
# Comparators                      : 22
#      11-bit comparator greatequal: 4
#      11-bit comparator less      : 18

Cell Usage :
# BELS                             : 256
#      GND                         : 1
#      INV                         : 19
#      LUT1                        : 6
#      LUT1_L                      : 28
#      LUT2                        : 15
#      LUT2_D                      : 1
#      LUT2_L                      : 19
#      LUT3                        : 13
#      LUT4                        : 41
#      LUT4_D                      : 2
#      LUT4_L                      : 18
#      MUXCY                       : 72
#      VCC                         : 1
#      XORCY                       : 20
# FlipFlops/Latches                : 25
#      FDC                         : 23
#      FDP                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 8
#      IBUF                        : 2
#      OBUF                        : 6
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     111  out of    768    14%  
 Number of Slice Flip Flops:            25  out of   1536     1%  
 Number of 4 input LUTs:               143  out of   1536     9%  
 Number of bonded IOBs:                  9  out of     96     9%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clock                              | BUFGP                  | 13    |
hsyncint:Q                         | NONE                   | 12    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.193ns (Maximum Frequency: 108.778MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 19.343ns
   Maximum combinational path delay: 13.220ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clock'
  Clock period: 8.144ns (frequency: 122.790MHz)
  Total number of paths / destination ports: 164 / 13
-------------------------------------------------------------------------
Delay:               8.144ns (Levels of Logic = 8)
  Source:            hcnt_5 (FF)
  Destination:       hcnt_10 (FF)
  Source Clock:      clock rising
  Destination Clock: clock rising

  Data Path: hcnt_5 to hcnt_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             22   1.085   2.970  hcnt_5 (hcnt_5)
     LUT1_L:I0->LO         1   0.549   0.000  hcnt_5_rt (hcnt_5_rt)
     MUXCY:S->O            1   0.659   0.000  vga_vl__n0005<5>cy (vga_vl__n0005<5>_cyo)
     MUXCY:CI->O           1   0.042   0.000  vga_vl__n0005<6>cy (vga_vl__n0005<6>_cyo)
     MUXCY:CI->O           1   0.042   0.000  vga_vl__n0005<7>cy (vga_vl__n0005<7>_cyo)
     MUXCY:CI->O           1   0.042   0.000  vga_vl__n0005<8>cy (vga_vl__n0005<8>_cyo)
     MUXCY:CI->O           0   0.042   0.000  vga_vl__n0005<9>cy (vga_vl__n0005<9>_cyo)
     XORCY:CI->O           1   0.420   1.035  vga_vl__n0005<10>_xor (_n0005<10>)
     LUT4_L:I0->LO         1   0.549   0.000  _n0000<10>2 (_n0000<10>)
     FDC:D                     0.709          hcnt_10
    ----------------------------------------
    Total                      8.144ns (4.139ns logic, 4.005ns route)
                                       (50.8% logic, 49.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'hsyncint:Q'
  Clock period: 9.193ns (frequency: 108.778MHz)
  Total number of paths / destination ports: 189 / 12
-------------------------------------------------------------------------
Delay:               9.193ns (Levels of Logic = 4)
  Source:            vcnt_6 (FF)
  Destination:       vcnt_10 (FF)
  Source Clock:      hsyncint:Q rising
  Destination Clock: hsyncint:Q rising

  Data Path: vcnt_6 to vcnt_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             12   1.085   2.160  vcnt_6 (vcnt_6)
     LUT2:I0->O            1   0.549   1.035  Ker443 (CHOICE1042)
     LUT4_D:I3->LO         1   0.549   0.100  Ker4417 (N768)
     LUT4:I2->O            9   0.549   1.908  Ker4452 (N441)
     LUT2_L:I1->LO         1   0.549   0.000  _n0002<5>1 (_n0002<5>)
     FDC:D                     0.709          vcnt_5
    ----------------------------------------
    Total                      9.193ns (3.990ns logic, 5.203ns route)
                                       (43.4% logic, 56.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'hsyncint:Q'
  Total number of paths / destination ports: 220 / 4
-------------------------------------------------------------------------
Offset:              19.298ns (Levels of Logic = 8)
  Source:            vcnt_3 (FF)
  Destination:       pixel<2> (PAD)
  Source Clock:      hsyncint:Q rising

  Data Path: vcnt_3 to pixel<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             12   1.085   2.160  vcnt_3 (vcnt_3)
     LUT4:I1->O            1   0.549   1.035  _n0013216 (CHOICE959)
     LUT4:I0->O            1   0.549   1.035  _n0013270_SW0 (N761)
     LUT4:I3->O            3   0.549   1.332  _n0013270 (_n0013)
     LUT3:I0->O            1   0.549   1.035  pixel<2>47 (CHOICE990)
     LUT3:I2->O            1   0.549   1.035  pixel<2>50 (CHOICE991)
     LUT4:I0->O            1   0.549   1.035  pixel<2>60 (CHOICE992)
     LUT2:I1->O            1   0.549   1.035  pixel<2>72 (pixel_2_OBUF)
     OBUF:I->O                 4.668          pixel_2_OBUF (pixel<2>)
    ----------------------------------------
    Total                     19.298ns (9.596ns logic, 9.702ns route)
                                       (49.7% logic, 50.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clock'
  Total number of paths / destination ports: 183 / 5
-------------------------------------------------------------------------
Offset:              19.343ns (Levels of Logic = 8)
  Source:            hcnt_4 (FF)
  Destination:       pixel<2> (PAD)
  Source Clock:      clock rising

  Data Path: hcnt_4 to pixel<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              9   1.085   1.908  hcnt_4 (hcnt_4)
     LUT2:I0->O            3   0.549   1.332  Ker471 (N471)
     LUT4:I2->O            1   0.549   1.035  _n0019219 (CHOICE845)
     LUT3:I2->O            1   0.549   1.035  _n0019232 (CHOICE848)
     LUT3:I2->O            3   0.549   1.332  _n0019241 (_n0019)
     LUT3:I1->O            1   0.549   1.035  pixel<2>19 (CHOICE980)
     LUT4:I3->O            1   0.549   1.035  pixel<2>60 (CHOICE992)
     LUT2:I1->O            1   0.549   1.035  pixel<2>72 (pixel_2_OBUF)
     OBUF:I->O                 4.668          pixel_2_OBUF (pixel<2>)
    ----------------------------------------
    Total                     19.343ns (9.596ns logic, 9.747ns route)
                                       (49.6% logic, 50.4% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 4 / 3
-------------------------------------------------------------------------
Delay:               13.220ns (Levels of Logic = 6)
  Source:            orient (PAD)
  Destination:       pixel<2> (PAD)

  Data Path: orient to pixel<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.776   1.440  orient_IBUF (orient_IBUF)
     LUT3:I2->O            1   0.549   1.035  pixel<2>47 (CHOICE990)
     LUT3:I2->O            1   0.549   1.035  pixel<2>50 (CHOICE991)
     LUT4:I0->O            1   0.549   1.035  pixel<2>60 (CHOICE992)
     LUT2:I1->O            1   0.549   1.035  pixel<2>72 (pixel_2_OBUF)
     OBUF:I->O                 4.668          pixel_2_OBUF (pixel<2>)
    ----------------------------------------
    Total                     13.220ns (7.640ns logic, 5.580ns route)
                                       (57.8% logic, 42.2% route)

=========================================================================
CPU : 15.01 / 16.54 s | Elapsed : 15.00 / 16.00 s
 
--> 

Total memory usage is 76804 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)