lcd0.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 2
 8-bit adder                       : 1
 8-bit subtractor                  : 1
# Counters                         : 1
 16-bit up counter                 : 1
# Registers                        : 31
 1-bit register                    : 29
 8-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <lcd0> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcd0, actual ratio is 6.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lcd0.ngr
Top Level Output File Name         : lcd0
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 15

Macro Statistics :
# Registers                        : 13
#      1-bit register              : 11
#      16-bit register             : 1
#      8-bit register              : 1
# Adders/Subtractors               : 2
#      16-bit adder                : 1
#      8-bit subtractor            : 1

Cell Usage :
# BELS                             : 123
#      GND                         : 1
#      INV                         : 9
#      LUT1                        : 14
#      LUT1_L                      : 2
#      LUT2                        : 9
#      LUT2_L                      : 1
#      LUT3                        : 2
#      LUT3_L                      : 1
#      LUT4                        : 15
#      LUT4_D                      : 3
#      LUT4_L                      : 20
#      MUXCY                       : 22
#      VCC                         : 1
#      XORCY                       : 23
# FlipFlops/Latches                : 61
#      FDC                         : 47
#      FDE                         : 11
#      FDP                         : 3
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 14
#      IBUF                        : 1
#      OBUF                        : 13
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      44  out of    768     5%  
 Number of Slice Flip Flops:            61  out of   1536     3%  
 Number of 4 input LUTs:                67  out of   1536     4%  
 Number of bonded IOBs:                 15  out of     96    15%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 16    |
div_cnt_15:Q                       | BUFG                   | 45    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.534ns (Maximum Frequency: 104.888MHz)
   Minimum input arrival time before clock: 5.406ns
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 8.398ns (frequency: 119.076MHz)
  Total number of paths / destination ports: 136 / 16
-------------------------------------------------------------------------
Delay:               8.398ns (Levels of Logic = 3)
  Source:            div_cnt_15 (FF)
  Destination:       div_cnt_15 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: div_cnt_15 to div_cnt_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   1.085   1.035  div_cnt_15 (div_cnt_151)
     BUFG:I->O            46   0.649   4.050  div_cnt_15_BUFG (div_cnt_15)
     LUT1_L:I0->LO         0   0.549   0.000  div_cnt_15_rt (div_cnt_15_rt)
     XORCY:LI->O           1   0.321   0.000  lcd0_div_cnt__n0000<15>_xor (div_cnt__n0000<15>)
     FDC:D                     0.709          div_cnt_15
    ----------------------------------------
    Total                      8.398ns (3.313ns logic, 5.085ns route)
                                       (39.4% logic, 60.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'div_cnt_15:Q'
  Clock period: 9.534ns (frequency: 104.888MHz)
  Total number of paths / destination ports: 450 / 46
-------------------------------------------------------------------------
Delay:               9.534ns (Levels of Logic = 4)
  Source:            mstate_FFd2 (FF)
  Destination:       lcd_rs (FF)
  Source Clock:      div_cnt_15:Q rising
  Destination Clock: div_cnt_15:Q rising

  Data Path: mstate_FFd2 to lcd_rs
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   1.085   1.566  mstate_FFd2 (mstate_FFd2)
     LUT3:I0->O            1   0.549   1.035  _n003814_SW0 (N194)
     LUT4:I3->O            9   0.549   1.908  _n003814 (_n0038)
     LUT4_D:I0->O          1   0.549   1.035  _n003747 (_n0037)
     LUT4_L:I1->LO         1   0.549   0.000  _n002717 (_n0027)
     FDE:D                     0.709          lcd_rs
    ----------------------------------------
    Total                      9.534ns (3.990ns logic, 5.544ns route)
                                       (41.9% logic, 58.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'div_cnt_15:Q'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              5.406ns (Levels of Logic = 2)
  Source:            nrst (PAD)
  Destination:       lcd_rst (FF)
  Destination Clock: div_cnt_15:Q rising

  Data Path: nrst to lcd_rst
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   0.776   2.160  nrst_IBUF (nrst_IBUF)
     LUT2:I1->O            1   0.549   1.035  _n00301 (_n0030)
     FDE:CE                    0.886          lcd_rst
    ----------------------------------------
    Total                      5.406ns (2.211ns logic, 3.195ns route)
                                       (40.9% logic, 59.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'div_cnt_15:Q'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            lcd_e (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      div_cnt_15:Q rising

  Data Path: lcd_e to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  lcd_e (lcd_e_OBUF)
     OBUF:I->O                 4.668          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 14.60 / 18.55 s | Elapsed : 15.00 / 17.00 s
 
--> 

Total memory usage is 74756 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)