lcd0.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 3.73 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 3.73 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: lcd0.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "lcd0.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "lcd0"
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : lcd0
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lcd0.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "lcd0.v"
Module <lcd0> compiled
No errors in compilation
Analysis of file <"lcd0.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <lcd0>.
	idle = <u>000001
	setfunction1_a = <u>000010
	setfunction1_b = <u>000011
	setfunction1_c = <u>000100
	setfunction2_a = <u>000101
	setfunction2_b = <u>000110
	setfunction2_c = <u>000111
	clear_a = <u>001000
	clear_b = <u>001001
	clear_c = <u>001010
	setmode_a = <u>001011
	setmode_b = <u>001100
	setmode_c = <u>001101
	setcursor_a = <u>001110
	setcursor_b = <u>001111
	setcursor_c = <u>010000
	setDDRAM_a = <u>010001
	setDDRAM_b = <u>010010
	setDDRAM_c = <u>010011
	writDDRAM_Ha = <u>010100
	writDDRAM_Hb = <u>010101
	writDDRAM_Hc = <u>010110
	writDDRAM_La = <u>010111
	writDDRAM_Lb = <u>011000
	writDDRAM_Lc = <u>011001
	delay = <u>011010
Module <lcd0> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <lcd0>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lcd0>.
    Related source file is "lcd0.v".
    Found finite state machine <FSM_0> for signal <mstate>.
    -----------------------------------------------------------------------
    | States             | 26                                             |
    | Transitions        | 28                                             |
    | Inputs             | 1                                              |
    | Outputs            | 25                                             |
    | Clock              | clk_div (rising_edge)                          |
    | Reset              | nrst (negative)                                |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <lcd_e>.
    Found 1-bit register for signal <lcd_rs>.
    Found 1-bit register for signal <lcd_rst>.
    Found 8-bit register for signal <data>.
    Found 8-bit subtractor for signal <$n0033>.
    Found 8-bit adder for signal <$n0034> created at line 213.
    Found 8-bit register for signal <cnt>.
    Found 16-bit up counter for signal <div_cnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  11 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <lcd0> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <mstate[1:26]> with speed1 encoding.
--------------------------------------
 State  | Encoding
--------------------------------------
 000001 | 10000000000000000000000000
 000010 | 01000000000000000000000000
 000011 | 00100000000000000000000000
 000100 | 00010000000000000000000000
 000101 | 00001000000000000000000000
 000110 | 00000100000000000000000000
 000111 | 00000010000000000000000000
 001000 | 00000001000000000000000000
 001001 | 00000000100000000000000000
 001010 | 00000000010000000000000000
 001011 | 00000000001000000000000000
 001100 | 00000000000100000000000000
 001101 | 00000000000010000000000000
 001110 | 00000000000001000000000000
 001111 | 00000000000000100000000000
 010000 | 00000000000000001000000000
 010001 | 00000000000000000010000000
 010010 | 00000000000000000000100000
 010011 | 00000000000000000000001000
 010100 | 00000000000000000000000100
 010101 | 00000000000000010000000000
 010110 | 00000000000000000100000000
 010111 | 00000000000000000001000000
 011000 | 00000000000000000000010000
 011001 | 00000000000000000000000010
 011010 | 00000000000000000000000001
--------------------------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report