keyscan.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise
e:\temp\spartan2\veriloge\interface\keyscan\keyscan.ise -intstyle ise -e 3 -l 3
-s 6 -xml keyscan keyscan.ncd -o keyscan.twr keyscan.pcf


Design file:              keyscan.ncd
Physical constraint file: keyscan.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
column<0>   |    5.694(R)|   -2.141(R)|clk_BUFGP         |   0.000|
column<1>   |    5.380(R)|   -1.842(R)|clk_BUFGP         |   0.000|
column<2>   |    5.428(R)|   -1.873(R)|clk_BUFGP         |   0.000|
column<3>   |    5.947(R)|   -2.136(R)|clk_BUFGP         |   0.000|
rst         |    2.796(R)|   -0.617(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dataout<0>  |   12.710(R)|clk_BUFGP         |   0.000|
dataout<1>  |   11.139(R)|clk_BUFGP         |   0.000|
dataout<2>  |   11.172(R)|clk_BUFGP         |   0.000|
dataout<3>  |   11.075(R)|clk_BUFGP         |   0.000|
dataout<4>  |   11.718(R)|clk_BUFGP         |   0.000|
dataout<5>  |   10.940(R)|clk_BUFGP         |   0.000|
dataout<6>  |   11.121(R)|clk_BUFGP         |   0.000|
dataout<7>  |   11.042(R)|clk_BUFGP         |   0.000|
row<0>      |    9.081(R)|clk_BUFGP         |   0.000|
row<1>      |    8.905(R)|clk_BUFGP         |   0.000|
row<2>      |    8.867(R)|clk_BUFGP         |   0.000|
row<3>      |    8.890(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    7.206|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Mar 14 15:19:54 2006
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Peak Memory Usage: 62 MB