serial.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

# Registers                        : 32
#      1-bit register              : 25
#      20-bit register             : 5
#      4-bit register              : 2
# Multiplexers                     : 1
#      4-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 7
#      20-bit adder                : 5
#      4-bit adder                 : 2
# Comparators                      : 5
#      3-bit comparator less       : 1
#      4-bit comparator greatequal : 1
#      4-bit comparator greater    : 1
#      4-bit comparator less       : 1
#      4-bit comparator lessequal  : 1

Cell Usage :
# BELS                             : 249
#      GND                         : 1
#      INV                         : 10
#      LUT1                        : 34
#      LUT2                        : 11
#      LUT2_D                      : 1
#      LUT2_L                      : 2
#      LUT3                        : 17
#      LUT3_D                      : 2
#      LUT3_L                      : 2
#      LUT4                        : 64
#      LUT4_D                      : 6
#      LUT4_L                      : 29
#      MUXCY                       : 34
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 34
# FlipFlops/Latches                : 79
#      FDC                         : 2
#      FDCE                        : 36
#      FDPE                        : 1
#      FDR                         : 16
#      FDRE                        : 24
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 21
#      IBUF                        : 3
#      OBUF                        : 18
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      93  out of    768    12%  
 Number of Slice Flip Flops:            79  out of   1536     5%  
 Number of 4 input LUTs:               168  out of   1536    10%  
 Number of bonded IOBs:                 22  out of     96    22%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clkbaud8x:Q                        | BUFG                   | 39    |
clk                                | BUFGP                  | 40    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.400ns (Maximum Frequency: 106.383MHz)
   Minimum input arrival time before clock: 8.106ns
   Maximum output required time after clock: 15.716ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clkbaud8x:Q'
  Clock period: 9.400ns (frequency: 106.383MHz)
  Total number of paths / destination ports: 489 / 75
-------------------------------------------------------------------------
Delay:               9.400ns (Levels of Logic = 4)
  Source:            state_tras_3 (FF)
  Destination:       txd_buf_3 (FF)
  Source Clock:      clkbaud8x:Q rising
  Destination Clock: clkbaud8x:Q rising

  Data Path: state_tras_3 to txd_buf_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            16   1.085   2.520  state_tras_3 (state_tras_3)
     LUT4_D:I1->O          7   0.549   1.755  Ker601 (N60)
     LUT4:I0->O            1   0.549   1.035  _n001527 (CHOICE302)
     LUT4_L:I1->LO         1   0.549   0.100  _n001563_SW0 (N926)
     LUT4_L:I1->LO         1   0.549   0.000  _n001563 (_n0015)
     FDCE:D                    0.709          txd_buf_3
    ----------------------------------------
    Total                      9.400ns (3.990ns logic, 5.410ns route)
                                       (42.4% logic, 57.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 9.019ns (frequency: 110.877MHz)
  Total number of paths / destination ports: 1135 / 99
-------------------------------------------------------------------------
Delay:               9.019ns (Levels of Logic = 3)
  Source:            cnt_delay_7 (FF)
  Destination:       cnt_delay_18 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_delay_7 to cnt_delay_18
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   1.085   1.206  cnt_delay_7 (cnt_delay_7)
     LUT2:I0->O            1   0.549   1.035  Ker593 (CHOICE174)
     LUT4_D:I0->O          3   0.549   1.332  Ker5963 (N59)
     LUT4:I2->O           10   0.549   1.980  _n00011_1 (_n00011)
     FDRE:R                    0.734          cnt_delay_18
    ----------------------------------------
    Total                      9.019ns (3.466ns logic, 5.553ns route)
                                       (38.4% logic, 61.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 43 / 43
-------------------------------------------------------------------------
Offset:              8.106ns (Levels of Logic = 5)
  Source:            key_input (PAD)
  Destination:       start_delaycnt (FF)
  Destination Clock: clk rising

  Data Path: key_input to start_delaycnt
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.776   1.206  key_input_IBUF (key_input_IBUF)
     LUT4:I0->O            1   0.549   1.035  _n014613 (CHOICE206)
     LUT4_L:I0->LO         1   0.549   0.000  _n014640_F (N963)
     MUXF5:I0->O           1   0.315   1.035  _n014640 (CHOICE215)
     LUT2:I1->O            2   0.549   1.206  _n014651 (_n0146)
     FDRE:CE                   0.886          start_delaycnt
    ----------------------------------------
    Total                      8.106ns (3.624ns logic, 4.482ns route)
                                       (44.7% logic, 55.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clkbaud8x:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              2.520ns (Levels of Logic = 1)
  Source:            rxd (PAD)
  Destination:       rxd_reg1 (FF)
  Destination Clock: clkbaud8x:Q rising

  Data Path: rxd to rxd_reg1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.776   1.035  rxd_IBUF (rxd_IBUF)
     FDC:D                     0.709          rxd_reg1
    ----------------------------------------
    Total                      2.520ns (1.485ns logic, 1.035ns route)
                                       (58.9% logic, 41.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkbaud8x:Q'
  Total number of paths / destination ports: 219 / 8
-------------------------------------------------------------------------
Offset:              15.716ns (Levels of Logic = 5)
  Source:            rxd_buf_2 (FF)
  Destination:       seg_data<7> (PAD)
  Source Clock:      clkbaud8x:Q rising

  Data Path: rxd_buf_2 to seg_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            18   1.085   2.700  rxd_buf_2 (rxd_buf_2)
     LUT4:I1->O            1   0.549   1.035  Ker1719 (CHOICE24)
     LUT4:I2->O            3   0.549   1.332  Ker1749 (N17)
     LUT4:I0->O            6   0.549   1.665  Ker36 (N36)
     LUT2:I1->O            1   0.549   1.035  seg_data<7>78 (seg_data_7_OBUF)
     OBUF:I->O                 4.668          seg_data_7_OBUF (seg_data<7>)
    ----------------------------------------
    Total                     15.716ns (7.949ns logic, 7.767ns route)
                                       (50.6% logic, 49.4% route)

=========================================================================
CPU : 15.36 / 16.28 s | Elapsed : 15.00 / 16.00 s
 
--> 

Total memory usage is 76804 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    1 (   0 filtered)