📄 serial.mrp
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Release 7.1i Map H.38Xilinx Mapping Report File for Design 'serial'Design Information------------------Command Line : D:/Xilinx/bin/nt/map.exe -ise
e:\temp\spartan2\veriloge\interface\uart\UART.ise -intstyle ise -p
xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o serial_map.ncd serial.ngd
serial.pcf Target Device : xc2s50Target Package : tq144Target Speed : -6Mapper Version : spartan2 -- $Revision: 1.26.6.3 $Mapped Date : Tue Mar 14 15:40:05 2006Design Summary--------------Number of errors: 0Number of warnings: 1Logic Utilization: Number of Slice Flip Flops: 78 out of 1,536 5% Number of 4 input LUTs: 136 out of 1,536 8%Logic Distribution: Number of occupied Slices: 103 out of 768 13% Number of Slices containing only related logic: 103 out of 103 100% Number of Slices containing unrelated logic: 0 out of 103 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 170 out of 1,536 11% Number used as logic: 136 Number used as a route-thru: 34 Number of bonded IOBs: 21 out of 92 22% IOB Flip Flops: 1 Number of GCLKs: 2 out of 4 50% Number of GCLKIOBs: 1 out of 4 25%Total equivalent gate count for design: 1,655Additional JTAG gate count for IOBs: 1,056Peak Memory Usage: 85 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol
"clkbaud8x_BUFG" (output signal=clkbaud8x) has a mix of clock and non-clock
loads. The non-clock loads are: Pin D of clkbaud8xSection 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| clk | GCLKIOB | INPUT | LVTTL | | | | | || en<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || en<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || en<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || en<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || en<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || en<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || en<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || en<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || key_input | IOB | INPUT | LVTTL | | | | | || lowbit | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || rst | IOB | INPUT | LVTTL | | | | | || rxd | IOB | INPUT | LVTTL | | | INFF | | IFD || seg_data<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || seg_data<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || seg_data<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || seg_data<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || seg_data<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || seg_data<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || seg_data<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || seg_data<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || txd | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 22Number of Equivalent Gates for Design = 1,655Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 2Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 53IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 1IOB Flip Flops = 1Unbonded IOBs = 0Bonded IOBs = 21XORs = 34CARRY_INITs = 18CARRY_SKIPs = 0CARRY_MUXes = 34Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULT_ANDs = 0MUXF5s + MUXF6s = 14 input LUTs used as Route-Thrus = 344 input LUTs = 136Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 52Slice Flip Flops = 78Slices = 103F6 Muxes = 0F5 Muxes = 1Number of LUT signals with 4 loads = 3Number of LUT signals with 3 loads = 5Number of LUT signals with 2 loads = 9Number of LUT signals with 1 load = 107NGM Average fanout of LUT = 1.86NGM Maximum fanout of LUT = 16NGM Average fanin for LUT = 3.5956Number of LUT symbols = 136⌨️ 快捷键说明
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