serial.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Number of signals used by logic mapping into function block:  29
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB8_1         (b)     
(unused)              0       0     0   5     FB8_2   91    I/O     
(unused)              0       0     0   5     FB8_3   95    I/O     
cnt_delay<9>          3       0     0   2     FB8_4   97    I/O     (b)
cnt_delay<7>          3       0     0   2     FB8_5   92    I/O     (b)
cnt_delay<6>          3       0     0   2     FB8_6   93    I/O     (b)
cnt_delay<5>          3       0     0   2     FB8_7         (b)     (b)
lowbit                0       0     0   5     FB8_8   94    I/O     O
cnt_delay<4>          3       0     0   2     FB8_9   96    I/O     (b)
cnt_delay<3>          3       0     0   2     FB8_10  101   I/O     (b)
cnt_delay<2>          3       0     0   2     FB8_11  98    I/O     (b)
cnt_delay<1>          3       0     0   2     FB8_12  100   I/O     I
cnt_delay<17>         3       0     0   2     FB8_13  103   I/O     (b)
cnt_delay<16>         3       0     0   2     FB8_14  102   I/O     (b)
cnt_delay<15>         3       0   \/1   1     FB8_15  104   I/O     (b)
seg_data<6>           6       1<-   0   0     FB8_16  107   I/O     O
cnt_delay<14>         3       0     0   2     FB8_17  105   I/O     (b)
cnt_delay<11>         3       0     0   2     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk               11: cnt_delay<1>      21: rxd_buf<0> 
  2: cnt_delay<0>      12: cnt_delay<2>      22: rxd_buf<1> 
  3: cnt_delay<10>     13: cnt_delay<3>      23: rxd_buf<2> 
  4: cnt_delay<11>     14: cnt_delay<4>      24: rxd_buf<3> 
  5: cnt_delay<12>     15: cnt_delay<5>      25: rxd_buf<4> 
  6: cnt_delay<13>     16: cnt_delay<6>      26: rxd_buf<5> 
  7: cnt_delay<14>     17: cnt_delay<7>      27: rxd_buf<6> 
  8: cnt_delay<15>     18: cnt_delay<8>      28: rxd_buf<7> 
  9: cnt_delay<16>     19: cnt_delay<9>      29: start_delaycnt 
 10: cnt_delay<17>     20: rst              

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
cnt_delay<9>         XX........XXXXXXXXXX........X........... 13
cnt_delay<7>         XX........XXXXXXX..X........X........... 11
cnt_delay<6>         XX........XXXXXX...X........X........... 10
cnt_delay<5>         XX........XXXXX....X........X........... 9
lowbit               ........................................ 0
cnt_delay<4>         XX........XXXX.....X........X........... 8
cnt_delay<3>         XX........XXX......X........X........... 7
cnt_delay<2>         XX........XX.......X........X........... 6
cnt_delay<1>         XX........X........X........X........... 5
cnt_delay<17>        XXXXXXXXXXXXXXXXXXXX........X........... 21
cnt_delay<16>        XXXXXXXXX.XXXXXXXXXX........X........... 20
cnt_delay<15>        XXXXXXXX..XXXXXXXXXX........X........... 19
seg_data<6>          ....................XXXXXXXX............ 8
cnt_delay<14>        XXXXXXX...XXXXXXXXXX........X........... 18
cnt_delay<11>        XXXX......XXXXXXXXXX........X........... 15
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********











































FTCPE FTCPE_clkbaud8x (clkbaud8x,clkbaud8x_T,clk,1'b0,1'b0);
assign clkbaud8x_T = ((!rst && clkbaud8x)
	|| (rst && div_reg[0] && !div_reg[10] && !div_reg[11] && 
	!div_reg[12] && !div_reg[13] && !div_reg[14] && div_reg[1] && 
	!div_reg[2] && !div_reg[3] && !div_reg[4] && !div_reg[5] && 
	!div_reg[6] && !div_reg[7] && div_reg[8] && !div_reg[9] && 
	!div_reg[15]));

FTCPE FTCPE_cnt_delay0 (cnt_delay[0],cnt_delay_T[0],clk,1'b0,1'b0);
assign cnt_delay_T[0] = ((rst && !start_delaycnt)
	|| (!rst && !cnt_delay[0])
	|| (!cnt_delay[0] && cnt_delay[10] && cnt_delay[12] && 
	cnt_delay[13] && cnt_delay[18] && cnt_delay[8] && !cnt_delay[11] && 
	!cnt_delay[14] && !cnt_delay[15] && !cnt_delay[16] && !cnt_delay[17] && 
	cnt_delay[19] && !cnt_delay[1] && !cnt_delay[2] && !cnt_delay[3] && 
	!cnt_delay[4] && !cnt_delay[5] && !cnt_delay[6] && !cnt_delay[7] && 
	!cnt_delay[9]));

FTCPE FTCPE_cnt_delay1 (cnt_delay[1],cnt_delay_T[1],clk,1'b0,1'b0);
assign cnt_delay_T[1] = ((!rst && cnt_delay[1])
	|| (rst && cnt_delay[0] && start_delaycnt));

FTCPE FTCPE_cnt_delay2 (cnt_delay[2],cnt_delay_T[2],clk,1'b0,1'b0);
assign cnt_delay_T[2] = ((!rst && cnt_delay[2])
	|| (rst && cnt_delay[0] && cnt_delay[1] && 
	start_delaycnt));

FTCPE FTCPE_cnt_delay3 (cnt_delay[3],cnt_delay_T[3],clk,1'b0,1'b0);
assign cnt_delay_T[3] = ((!rst && cnt_delay[3])
	|| (rst && cnt_delay[0] && cnt_delay[1] && 
	cnt_delay[2] && start_delaycnt));

FTCPE FTCPE_cnt_delay4 (cnt_delay[4],cnt_delay_T[4],clk,1'b0,1'b0);
assign cnt_delay_T[4] = ((!rst && cnt_delay[4])
	|| (rst && cnt_delay[0] && cnt_delay[1] && 
	cnt_delay[2] && cnt_delay[3] && start_delaycnt));

FTCPE FTCPE_cnt_delay5 (cnt_delay[5],cnt_delay_T[5],clk,1'b0,1'b0);
assign cnt_delay_T[5] = ((!rst && cnt_delay[5])
	|| (rst && cnt_delay[0] && cnt_delay[1] && 
	cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && start_delaycnt));

FTCPE FTCPE_cnt_delay6 (cnt_delay[6],cnt_delay_T[6],clk,1'b0,1'b0);
assign cnt_delay_T[6] = ((!rst && cnt_delay[6])
	|| (rst && cnt_delay[0] && cnt_delay[1] && 
	cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && cnt_delay[5] && 
	start_delaycnt));

FTCPE FTCPE_cnt_delay7 (cnt_delay[7],cnt_delay_T[7],clk,1'b0,1'b0);
assign cnt_delay_T[7] = ((!rst && cnt_delay[7])
	|| (rst && cnt_delay[0] && cnt_delay[1] && 
	cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && cnt_delay[5] && 
	cnt_delay[6] && start_delaycnt));

FTCPE FTCPE_cnt_delay8 (cnt_delay[8],cnt_delay_T[8],clk,1'b0,1'b0);
assign cnt_delay_T[8] = ((!rst && cnt_delay[8])
	|| (rst && cnt_delay[0] && cnt_delay[1] && 
	cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && cnt_delay[5] && 
	cnt_delay[6] && cnt_delay[7] && start_delaycnt)
	|| (!cnt_delay[0] && cnt_delay[10] && cnt_delay[12] && 
	cnt_delay[13] && cnt_delay[18] && cnt_delay[8] && !cnt_delay[11] && 
	!cnt_delay[14] && !cnt_delay[15] && !cnt_delay[16] && !cnt_delay[17] && 
	cnt_delay[19] && !cnt_delay[1] && !cnt_delay[2] && !cnt_delay[3] && 
	!cnt_delay[4] && !cnt_delay[5] && !cnt_delay[6] && !cnt_delay[7] && 
	!cnt_delay[9] && start_delaycnt));

FTCPE FTCPE_cnt_delay9 (cnt_delay[9],cnt_delay_T[9],clk,1'b0,1'b0);
assign cnt_delay_T[9] = ((!rst && cnt_delay[9])
	|| (rst && cnt_delay[0] && cnt_delay[8] && 
	cnt_delay[1] && cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && 
	cnt_delay[5] && cnt_delay[6] && cnt_delay[7] && start_delaycnt));

FTCPE FTCPE_cnt_delay10 (cnt_delay[10],cnt_delay_T[10],clk,1'b0,1'b0);
assign cnt_delay_T[10] = ((!rst && cnt_delay[10])
	|| (rst && cnt_delay[0] && cnt_delay[8] && 
	cnt_delay[1] && cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && 
	cnt_delay[5] && cnt_delay[6] && cnt_delay[7] && cnt_delay[9] && 
	start_delaycnt)
	|| (!cnt_delay[0] && cnt_delay[10] && cnt_delay[12] && 
	cnt_delay[13] && cnt_delay[18] && cnt_delay[8] && !cnt_delay[11] && 
	!cnt_delay[14] && !cnt_delay[15] && !cnt_delay[16] && !cnt_delay[17] && 
	cnt_delay[19] && !cnt_delay[1] && !cnt_delay[2] && !cnt_delay[3] && 
	!cnt_delay[4] && !cnt_delay[5] && !cnt_delay[6] && !cnt_delay[7] && 
	!cnt_delay[9] && start_delaycnt));

FTCPE FTCPE_cnt_delay11 (cnt_delay[11],cnt_delay_T[11],clk,1'b0,1'b0);
assign cnt_delay_T[11] = ((!rst && cnt_delay[11])
	|| (rst && cnt_delay[0] && cnt_delay[10] && 
	cnt_delay[8] && cnt_delay[1] && cnt_delay[2] && cnt_delay[3] && 
	cnt_delay[4] && cnt_delay[5] && cnt_delay[6] && cnt_delay[7] && 
	cnt_delay[9] && start_delaycnt));

FTCPE FTCPE_cnt_delay12 (cnt_delay[12],cnt_delay_T[12],clk,1'b0,1'b0);
assign cnt_delay_T[12] = ((!rst && cnt_delay[12])
	|| (rst && cnt_delay[0] && cnt_delay[10] && 
	cnt_delay[8] && cnt_delay[11] && cnt_delay[1] && cnt_delay[2] && 
	cnt_delay[3] && cnt_delay[4] && cnt_delay[5] && cnt_delay[6] && 
	cnt_delay[7] && cnt_delay[9] && start_delaycnt)
	|| (!cnt_delay[0] && cnt_delay[10] && cnt_delay[12] && 
	cnt_delay[13] && cnt_delay[18] && cnt_delay[8] && !cnt_delay[11] && 
	!cnt_delay[14] && !cnt_delay[15] && !cnt_delay[16] && !cnt_delay[17] && 
	cnt_delay[19] && !cnt_delay[1] && !cnt_delay[2] && !cnt_delay[3] && 
	!cnt_delay[4] && !cnt_delay[5] && !cnt_delay[6] && !cnt_delay[7] && 
	!cnt_delay[9] && start_delaycnt));

FTCPE FTCPE_cnt_delay13 (cnt_delay[13],cnt_delay_T[13],clk,1'b0,1'b0);
assign cnt_delay_T[13] = ((!rst && cnt_delay[13])
	|| (rst && cnt_delay[0] && cnt_delay[10] && 
	cnt_delay[12] && cnt_delay[8] && cnt_delay[11] && cnt_delay[1] && 
	cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && cnt_delay[5] && 
	cnt_delay[6] && cnt_delay[7] && cnt_delay[9] && start_delaycnt)
	|| (!cnt_delay[0] && cnt_delay[10] && cnt_delay[12] && 
	cnt_delay[13] && cnt_delay[18] && cnt_delay[8] && !cnt_delay[11] && 
	!cnt_delay[14] && !cnt_delay[15] && !cnt_delay[16] && !cnt_delay[17] && 
	cnt_delay[19] && !cnt_delay[1] && !cnt_delay[2] && !cnt_delay[3] && 
	!cnt_delay[4] && !cnt_delay[5] && !cnt_delay[6] && !cnt_delay[7] && 
	!cnt_delay[9] && start_delaycnt));

FTCPE FTCPE_cnt_delay14 (cnt_delay[14],cnt_delay_T[14],clk,1'b0,1'b0);
assign cnt_delay_T[14] = ((!rst && cnt_delay[14])
	|| (rst && cnt_delay[0] && cnt_delay[10] && 
	cnt_delay[12] && cnt_delay[13] && cnt_delay[8] && cnt_delay[11] && 
	cnt_delay[1] && cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && 
	cnt_delay[5] && cnt_delay[6] && cnt_delay[7] && cnt_delay[9] && 
	start_delaycnt));

FTCPE FTCPE_cnt_delay15 (cnt_delay[15],cnt_delay_T[15],clk,1'b0,1'b0);
assign cnt_delay_T[15] = ((!rst && cnt_delay[15])
	|| (rst && cnt_delay[0] && cnt_delay[10] && 
	cnt_delay[12] && cnt_delay[13] && cnt_delay[8] && cnt_delay[11] && 
	cnt_delay[14] && cnt_delay[1] && cnt_delay[2] && cnt_delay[3] && 
	cnt_delay[4] && cnt_delay[5] && cnt_delay[6] && cnt_delay[7] && 
	cnt_delay[9] && start_delaycnt));

FTCPE FTCPE_cnt_delay16 (cnt_delay[16],cnt_delay_T[16],clk,1'b0,1'b0);
assign cnt_delay_T[16] = ((!rst && cnt_delay[16])
	|| (rst && cnt_delay[0] && cnt_delay[10] && 
	cnt_delay[12] && cnt_delay[13] && cnt_delay[8] && cnt_delay[11] && 
	cnt_delay[14] && cnt_delay[15] && cnt_delay[1] && cnt_delay[2] && 
	cnt_delay[3] && cnt_delay[4] && cnt_delay[5] && cnt_delay[6] && 
	cnt_delay[7] && cnt_delay[9] && start_delaycnt));

FTCPE FTCPE_cnt_delay17 (cnt_delay[17],cnt_delay_T[17],clk,1'b0,1'b0);
assign cnt_delay_T[17] = ((!rst && cnt_delay[17])
	|| (rst && cnt_delay[0] && cnt_delay[10] && 
	cnt_delay[12] && cnt_delay[13] && cnt_delay[8] && cnt_delay[11] && 
	cnt_delay[14] && cnt_delay[15] && cnt_delay[16] && cnt_delay[1] && 
	cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && cnt_delay[5] && 
	cnt_delay[6] && cnt_delay[7] && cnt_delay[9] && start_delaycnt));

FTCPE FTCPE_cnt_delay18 (cnt_delay[18],cnt_delay_T[18],clk,1'b0,1'b0);
assign cnt_delay_T[18] = ((!rst && cnt_delay[18])
	|| (rst && cnt_delay[0] && cnt_delay[10] && 
	cnt_delay[12] && cnt_delay[13] && cnt_delay[8] && cnt_delay[11] && 
	cnt_delay[14] && cnt_delay[15] && cnt_delay[16] && cnt_delay[17] && 
	cnt_delay[1] && cnt_delay[2] && cnt_delay[3] && cnt_delay[4] && 
	cnt_delay[5] && cnt_delay[6] && cnt_delay[7] && cnt_delay[9] && 
	start_delaycnt)
	|| (!cnt_delay[0] && cnt_delay[10] && cnt_delay[12] && 
	cnt_delay[13] && cnt_delay[18] && cnt_delay[8] && !cnt_delay[11] && 
	!cnt_delay[14] && !cnt_delay[15] && !cnt_delay[16] && !cnt_delay[17] &&