serial.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

	state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & recstart & 
	div8_rec_reg<2>;
   recstart.CLK = clkbaud8x;
   recstart.AR = !rst;
    recstart.EXP  =  !rxd_buf<1> & rxd_buf<2> & rxd_buf<0> & 
	rxd_buf<4> & rxd_buf<5> & !rxd_buf<6> & !rxd_buf<3> & 
	!rxd_buf<7>

MACROCELL | 5 | 12 | div8_rec_reg<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 23 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 6 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16
INPUTS | 5 | div8_rec_reg<0>  | div8_rec_reg<1>  | clkbaud8x  | rst  | recstart
INPUTMC | 4 | 2 | 3 | 5 | 13 | 1 | 13 | 5 | 6
INPUTP | 1 | 79
EQ | 4 | 
   div8_rec_reg<2>.T = div8_rec_reg<0> & div8_rec_reg<1>;
   div8_rec_reg<2>.CLK = clkbaud8x;
   div8_rec_reg<2>.AR = !rst;
   div8_rec_reg<2>.CE = recstart;

MACROCELL | 2 | 11 | div8_tras_reg<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 33 | 6 | 8 | 2 | 5 | 2 | 8 | 2 | 4 | 2 | 14 | 1 | 15 | 1 | 14 | 1 | 0 | 6 | 13 | 6 | 16 | 6 | 11 | 6 | 5 | 2 | 1 | 6 | 2 | 2 | 7 | 2 | 17 | 2 | 0 | 2 | 2 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 15 | 2 | 16 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 6 | 6 | 7 | 6 | 9 | 6 | 10 | 6 | 12 | 6 | 15
INPUTS | 5 | div8_tras_reg<0>  | div8_tras_reg<1>  | clkbaud8x  | rst  | trasstart
INPUTMC | 4 | 2 | 2 | 2 | 12 | 1 | 13 | 6 | 17
INPUTP | 1 | 79
EQ | 4 | 
   div8_tras_reg<2>.T = div8_tras_reg<0> & div8_tras_reg<1>;
   div8_tras_reg<2>.CLK = clkbaud8x;
   div8_tras_reg<2>.AR = !rst;
   div8_tras_reg<2>.CE = trasstart;

MACROCELL | 2 | 17 | txd_buf<6>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 8 | 2 | 7 | 2 | 17 | 2 | 6 | 2 | 8 | 2 | 9 | 2 | 15 | 2 | 16 | 2 | 0
INPUTS | 15 | key_entry2  | txd_buf<6>  | key_entry1  | state_tras<2>  | state_tras<3>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | state_tras<1>  | state_tras<0>  | txd_buf<4>  | txd_buf<5>  | clkbaud8x  | rst  | EXP13_.EXP
INPUTMC | 14 | 2 | 10 | 2 | 17 | 0 | 8 | 2 | 5 | 2 | 4 | 2 | 2 | 2 | 12 | 2 | 11 | 2 | 9 | 2 | 15 | 2 | 1 | 2 | 7 | 1 | 13 | 2 | 16
INPUTP | 1 | 79
EXPORTS | 1 | 2 | 0
IMPORTS | 1 | 2 | 16
EQ | 29 | 
   txd_buf<6>.T = !key_entry2 & !txd_buf<6> & key_entry1
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2> & txd_buf<6>
;Imported pterms FB3_17
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2> & txd_buf<6>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2> & txd_buf<6>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2> & !txd_buf<6>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2> & txd_buf<6>
	# state_tras<2> & state_tras<1> & state_tras<0> & 
	key_entry2 & send_state<1> & send_state<2> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2> & txd_buf<6>
;Imported pterms FB3_16
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2> & !txd_buf<6>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<2> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2> & !txd_buf<6>;
   txd_buf<6>.CLK = clkbaud8x;
   txd_buf<6>.AR = !rst;
    txd_buf<6>.EXP  =  !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<4> & div8_tras_reg<0> & 
	!txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2>

MACROCELL | 1 | 13 | clkbaud8x
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 40 | 6 | 9 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 3 | 13 | 3 | 17 | 3 | 15 | 2 | 10 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 1 | 15 | 1 | 14 | 5 | 17 | 1 | 0 | 6 | 14 | 5 | 15 | 5 | 2 | 5 | 0 | 6 | 17 | 5 | 4 | 6 | 12 | 6 | 6 | 2 | 1 | 2 | 3 | 2 | 2 | 5 | 5 | 6 | 3 | 2 | 7 | 5 | 13 | 2 | 12 | 5 | 6 | 5 | 12 | 2 | 11 | 2 | 17 | 1 | 13 | 2 | 13 | 2 | 6
INPUTS | 19 | rst  | div_reg<0>  | div_reg<10>  | div_reg<11>  | div_reg<12>  | div_reg<13>  | div_reg<14>  | div_reg<1>  | div_reg<2>  | div_reg<3>  | div_reg<4>  | div_reg<5>  | div_reg<6>  | div_reg<7>  | div_reg<8>  | div_reg<9>  | div_reg<15>  | clkbaud8x  | clk
INPUTMC | 17 | 0 | 7 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 9 | 1 | 8 | 0 | 9 | 1 | 17 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 1 | 2 | 1 | 16 | 1 | 1 | 1 | 7 | 1 | 13
INPUTP | 2 | 79 | 143
EQ | 7 | 
   clkbaud8x.T = !rst & clkbaud8x
	# rst & div_reg<0> & !div_reg<10> & !div_reg<11> & 
	!div_reg<12> & !div_reg<13> & !div_reg<14> & div_reg<1> & 
	!div_reg<2> & !div_reg<3> & !div_reg<4> & !div_reg<5> & 
	!div_reg<6> & !div_reg<7> & div_reg<8> & !div_reg<9> & 
	!div_reg<15>;
   clkbaud8x.CLK = clk;

MACROCELL | 0 | 17 | cnt_delay<0>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 22 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 17 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10 | 0 | 8
INPUTS | 23 | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | rst  | start_delaycnt  | clk
INPUTMC | 21 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 17 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10
INPUTP | 2 | 79 | 143
EQ | 9 | 
   !cnt_delay<0>.T = rst & !start_delaycnt
	# !rst & !cnt_delay<0>
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9>;
   cnt_delay<0>.CLK = clk;

MACROCELL | 0 | 16 | cnt_delay<10>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 14 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 17 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 0 | 10 | 0 | 8
INPUTS | 23 | rst  | cnt_delay<10>  | cnt_delay<0>  | cnt_delay<8>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk
INPUTMC | 21 | 0 | 16 | 0 | 17 | 0 | 11 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10 | 0 | 15 | 0 | 14 | 0 | 13 | 7 | 17 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12
INPUTP | 2 | 79 | 143
EQ | 12 | 
   cnt_delay<10>.T = !rst & cnt_delay<10>
	# rst & cnt_delay<0> & cnt_delay<8> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9> & 
	start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<10>.CLK = clk;

MACROCELL | 0 | 15 | cnt_delay<12>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 13 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 0 | 10 | 0 | 8
INPUTS | 23 | rst  | cnt_delay<12>  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk
INPUTMC | 21 | 0 | 15 | 0 | 17 | 0 | 16 | 0 | 11 | 7 | 17 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10 | 0 | 14 | 0 | 13 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12
INPUTP | 2 | 79 | 143
EQ | 12 | 
   cnt_delay<12>.T = !rst & cnt_delay<12>
	# rst & cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<8> & cnt_delay<11> & cnt_delay<1> & cnt_delay<2> & 
	cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & 
	cnt_delay<7> & cnt_delay<9> & start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<12>.CLK = clk;

MACROCELL | 0 | 14 | cnt_delay<13>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 13 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 0 | 10 | 0 | 8
INPUTS | 23 | rst  | cnt_delay<13>  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<18>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | clk
INPUTMC | 21 | 0 | 14 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 11 | 7 | 17 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10 | 0 | 13 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12
INPUTP | 2 | 79 | 143
EQ | 12 | 
   cnt_delay<13>.T = !rst & cnt_delay<13>
	# rst & cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<8> & cnt_delay<11> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7> & cnt_delay<9> & start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<13>.CLK = clk;

MACROCELL | 0 | 13 | cnt_delay<18>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 9 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 0 | 12 | 0 | 10 | 0 | 8
INPUTS | 23 | rst  | cnt_delay<18>  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<19>  | clk
INPUTMC | 21 | 0 | 13 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 11 | 7 | 17 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10 | 0 | 12
INPUTP | 2 | 79 | 143
EQ | 14 | 
   cnt_delay<18>.T = !rst & cnt_delay<18>
	# rst & cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & 
	cnt_delay<14> & cnt_delay<15> & cnt_delay<16> & cnt_delay<17> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9> & 
	start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<18>.CLK = clk;

MACROCELL | 0 | 11 | cnt_delay<8>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 15 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 17 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 7 | 3 | 0 | 10 | 0 | 8
INPUTS | 23 | rst  | cnt_delay<8>  | cnt_delay<0>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | start_delaycnt  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<9>  | clk
INPUTMC | 21 | 0 | 11 | 0 | 17 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 0 | 10 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 7 | 17 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 7 | 3
INPUTP | 2 | 79 | 143
EQ | 11 | 
   cnt_delay<8>.T = !rst & cnt_delay<8>
	# rst & cnt_delay<0> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7> & start_delaycnt
	# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> & 
	!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> & 
	cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> & 
	!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> & 
	!cnt_delay<9> & start_delaycnt;
   cnt_delay<8>.CLK = clk;

MACROCELL | 7 | 17 | cnt_delay<11>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 14 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 17 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 0 | 10 | 0 | 8
INPUTS | 15 | rst  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<8>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<11>  | clk
INPUTMC | 13 | 0 | 17 | 0 | 16 | 0 | 11 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10 | 7 | 17
INPUTP | 2 | 79 | 143
EQ | 6 | 
   cnt_delay<11>.T = !rst & cnt_delay<11>
	# rst & cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<8> & cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & 
	cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & 
	cnt_delay<9> & start_delaycnt;
   cnt_delay<11>.CLK = clk;

MACROCELL | 7 | 16 | cnt_delay<14>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 13 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 16 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 0 | 10 | 0 | 8
INPUTS | 18 | rst  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<14>  | clk
INPUTMC | 16 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 11 | 7 | 17 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10 | 7 | 16
INPUTP | 2 | 79 | 143
EQ | 7 | 
   cnt_delay<14>.T = !rst & cnt_delay<14>
	# rst & cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9> & 
	start_delaycnt;
   cnt_delay<14>.CLK = clk;

MACROCELL | 7 | 14 | cnt_delay<15>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 13 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 11 | 7 | 14 | 7 | 13 | 7 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 7 | 15
INPUTS | 27 | rst  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | start_delaycnt  | cnt_delay<15>  | clk  | rxd_buf<1>  | rxd_buf<2>  | rxd_buf<0>  | rxd_buf<4>  | rxd_buf<5>  | rxd_buf<6>  | rxd_buf<3>  | rxd_buf<7>
INPUTMC | 25 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 11 | 7 | 17 | 7 | 16 | 7 | 11 | 7 | 10 | 7 | 9 | 7 | 8 | 7 | 6 | 7 | 5 | 7 | 4 | 7 | 3 | 0 | 10 | 7 | 14 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 7 | 15
EQ | 10