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📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
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	!state_tras<3> & !state_tras<0> & send_state<1> & send_state<2> & 
	send_state<0>

MACROCELL | 2 | 1 | txd_buf<4>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 6 | 6 | 4 | 2 | 1 | 2 | 0 | 2 | 2 | 2 | 17 | 6 | 3
INPUTS | 14 | key_entry2  | txd_buf<4>  | key_entry1  | state_tras<2>  | state_tras<3>  | div8_tras_reg<0>  | txd_buf<5>  | div8_tras_reg<1>  | div8_tras_reg<2>  | state_tras<1>  | EXP10_.EXP  | clkbaud8x  | rst  | div8_tras_reg<0>.EXP
INPUTMC | 13 | 2 | 10 | 2 | 1 | 0 | 8 | 2 | 5 | 2 | 4 | 2 | 2 | 2 | 7 | 2 | 12 | 2 | 11 | 2 | 9 | 2 | 0 | 1 | 13 | 2 | 2
INPUTP | 1 | 79
IMPORTS | 2 | 2 | 0 | 2 | 2
EQ | 36 | 
   txd_buf<4>.T = !key_entry2 & !txd_buf<4> & key_entry1
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	!txd_buf<4> & div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	!txd_buf<4> & div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB3_1
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & !txd_buf<5> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & !txd_buf<5> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & !txd_buf<5> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	!txd_buf<4> & div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB3_18
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<4> & div8_tras_reg<0> & 
	!txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB3_3
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<4> & div8_tras_reg<0> & txd_buf<5> & 
	div8_tras_reg<1> & div8_tras_reg<2>;
   txd_buf<4>.CLK = clkbaud8x;
   txd_buf<4>.AR = !rst;

MACROCELL | 2 | 3 | div8_rec_reg<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 25 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 13 | 5 | 6 | 5 | 12 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16
INPUTS | 3 | clkbaud8x  | rst  | recstart
INPUTMC | 2 | 1 | 13 | 5 | 6
INPUTP | 1 | 79
EQ | 4 | 
   div8_rec_reg<0>.T = Vcc;
   div8_rec_reg<0>.CLK = clkbaud8x;
   div8_rec_reg<0>.AR = !rst;
   div8_rec_reg<0>.CE = recstart;

MACROCELL | 2 | 2 | div8_tras_reg<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 33 | 6 | 8 | 2 | 5 | 2 | 8 | 2 | 4 | 2 | 14 | 1 | 15 | 1 | 14 | 1 | 0 | 6 | 14 | 6 | 16 | 6 | 12 | 6 | 6 | 2 | 1 | 6 | 2 | 2 | 7 | 2 | 12 | 2 | 11 | 2 | 17 | 2 | 0 | 2 | 2 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 15 | 2 | 16 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 7 | 6 | 9 | 6 | 10 | 6 | 15
INPUTS | 13 | clkbaud8x  | rst  | trasstart  | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | txd_buf<4>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | txd_buf<5>
INPUTMC | 12 | 1 | 13 | 6 | 17 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 2 | 10 | 2 | 1 | 2 | 2 | 2 | 12 | 2 | 11 | 2 | 7
INPUTP | 1 | 79
EXPORTS | 1 | 2 | 1
EQ | 10 | 
   div8_tras_reg<0>.T = Vcc;
   div8_tras_reg<0>.CLK = clkbaud8x;
   div8_tras_reg<0>.AR = !rst;
   div8_tras_reg<0>.CE = trasstart;
    div8_tras_reg<0>.EXP  =  !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<4> & div8_tras_reg<0> & txd_buf<5> & 
	div8_tras_reg<1> & div8_tras_reg<2>

MACROCELL | 5 | 5 | recstart_tmp
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 3 | 5 | 15 | 5 | 5 | 5 | 6
INPUTS | 9 | state_rec<0>  | state_rec<1>  | state_rec<2>  | state_rec<3>  | recstart_tmp  | rxd_reg1  | rxd_reg2  | clkbaud8x  | rst
INPUTMC | 8 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 5 | 2 | 13 | 2 | 6 | 1 | 13
INPUTP | 1 | 79
EQ | 6 | 
   recstart_tmp.T = !state_rec<0> & !state_rec<1> & !state_rec<2> & 
	!state_rec<3> & recstart_tmp
	# !state_rec<0> & !state_rec<1> & !state_rec<2> & 
	!state_rec<3> & !rxd_reg1 & rxd_reg2;
   recstart_tmp.CLK = clkbaud8x;
   recstart_tmp.AR = !rst;

MACROCELL | 6 | 3 | txd_buf<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 5 | 6 | 1 | 6 | 2 | 6 | 0 | 6 | 15 | 6 | 4
INPUTS | 15 | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | txd_buf<4>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | send_state<2>  | send_state<0>  | send_state<1>  | EXP21_.EXP  | clkbaud8x  | rst
INPUTMC | 14 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 2 | 10 | 2 | 1 | 2 | 2 | 2 | 12 | 2 | 11 | 1 | 14 | 1 | 0 | 1 | 15 | 6 | 2 | 1 | 13
INPUTP | 1 | 79
EXPORTS | 1 | 6 | 4
IMPORTS | 1 | 6 | 2
EQ | 52 | 
   txd_buf<1>.T = ;Imported pterms FB7_3
	  !key_entry2 & !txd_buf<1> & key_entry1
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	txd_buf<2> & div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	!txd_buf<2> & div8_tras_reg<0> & txd_buf<1> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	!txd_buf<2> & div8_tras_reg<0> & txd_buf<1> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	!txd_buf<2> & div8_tras_reg<0> & txd_buf<1> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB7_2
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	txd_buf<2> & div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	txd_buf<2> & div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & div8_tras_reg<0> & txd_buf<1> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<2> & div8_tras_reg<0> & txd_buf<1> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & div8_tras_reg<0> & 
	txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB7_1
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<2> & div8_tras_reg<0> & 
	txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<2> & div8_tras_reg<0> & 
	!txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & !send_state<2> & 
	div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>;
   txd_buf<1>.CLK = clkbaud8x;
   txd_buf<1>.AR = !rst;
    txd_buf<1>.EXP  =  !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<2> & send_state<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & send_state<2> & 
	!send_state<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>

MACROCELL | 2 | 7 | txd_buf<5>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 8 | 2 | 1 | 2 | 7 | 2 | 0 | 2 | 2 | 2 | 6 | 2 | 8 | 2 | 9 | 2 | 17
INPUTS | 14 | key_entry2  | txd_buf<5>  | key_entry1  | state_tras<2>  | state_tras<3>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | txd_buf<6>  | state_tras<1>  | rxd_reg2.EXP  | EXP11_.EXP  | clkbaud8x  | rst
INPUTMC | 13 | 2 | 10 | 2 | 7 | 0 | 8 | 2 | 5 | 2 | 4 | 2 | 2 | 2 | 12 | 2 | 11 | 2 | 17 | 2 | 9 | 2 | 6 | 2 | 8 | 1 | 13
INPUTP | 1 | 79
IMPORTS | 2 | 2 | 6 | 2 | 8
EQ | 42 | 
   txd_buf<5>.T = !key_entry2 & !txd_buf<5> & key_entry1
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2> & 
	txd_buf<6>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2> & 
	txd_buf<6>
;Imported pterms FB3_7
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2> & 
	!txd_buf<6>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2> & 
	!txd_buf<6>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2> & 
	txd_buf<6>
;Imported pterms FB3_9
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2> & 
	!txd_buf<6>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & div8_tras_reg<0> & txd_buf<5> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & 
	div8_tras_reg<2> & !txd_buf<6>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & div8_tras_reg<0> & 
	!txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<2> & div8_tras_reg<0> & 
	!txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB3_10
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & div8_tras_reg<0> & !txd_buf<5> & 
	div8_tras_reg<1> & div8_tras_reg<2> & txd_buf<6>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2>;
   txd_buf<5>.CLK = clkbaud8x;
   txd_buf<5>.AR = !rst;

MACROCELL | 5 | 13 | div8_rec_reg<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 24 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 6 | 5 | 12 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16
INPUTS | 4 | div8_rec_reg<0>  | clkbaud8x  | rst  | recstart
INPUTMC | 3 | 2 | 3 | 1 | 13 | 5 | 6
INPUTP | 1 | 79
EQ | 4 | 
   div8_rec_reg<1>.T = div8_rec_reg<0>;
   div8_rec_reg<1>.CLK = clkbaud8x;
   div8_rec_reg<1>.AR = !rst;
   div8_rec_reg<1>.CE = recstart;

MACROCELL | 2 | 12 | div8_tras_reg<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 34 | 6 | 8 | 2 | 5 | 2 | 8 | 2 | 4 | 2 | 14 | 1 | 15 | 1 | 14 | 1 | 0 | 6 | 14 | 6 | 16 | 6 | 11 | 6 | 5 | 2 | 1 | 6 | 2 | 2 | 7 | 2 | 11 | 2 | 17 | 2 | 0 | 2 | 2 | 2 | 6 | 2 | 9 | 2 | 10 | 2 | 15 | 2 | 16 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 6 | 6 | 7 | 6 | 9 | 6 | 10 | 6 | 12 | 6 | 15
INPUTS | 4 | div8_tras_reg<0>  | clkbaud8x  | rst  | trasstart
INPUTMC | 3 | 2 | 2 | 1 | 13 | 6 | 17
INPUTP | 1 | 79
EQ | 4 | 
   div8_tras_reg<1>.T = div8_tras_reg<0>;
   div8_tras_reg<1>.CLK = clkbaud8x;
   div8_tras_reg<1>.AR = !rst;
   div8_tras_reg<1>.CE = trasstart;

MACROCELL | 5 | 6 | recstart
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 5 | 2 | 3 | 5 | 13 | 5 | 6 | 5 | 12 | 5 | 7
INPUTS | 19 | state_rec<0>  | state_rec<1>  | state_rec<2>  | state_rec<3>  | recstart_tmp  | recstart  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst  | rxd_buf<1>  | rxd_buf<2>  | rxd_buf<0>  | rxd_buf<4>  | rxd_buf<5>  | rxd_buf<6>  | rxd_buf<3>  | rxd_buf<7>
INPUTMC | 18 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 5 | 5 | 6 | 2 | 3 | 5 | 13 | 5 | 12 | 1 | 13 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17
INPUTP | 1 | 79
EXPORTS | 1 | 5 | 7
EQ | 10 | 
   recstart.T = !state_rec<0> & !state_rec<1> & !state_rec<2> & 
	!state_rec<3> & recstart_tmp & !recstart
	# state_rec<0> & !state_rec<1> & !state_rec<2> &
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