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📄 serial.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
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IMPORTS | 2 | 6 | 13 | 6 | 15
EQ | 33 | 
   !txd_buf<0>.D = key_entry2 & !txd_buf<0> & !div8_tras_reg<0>
	# key_entry2 & !txd_buf<0> & !div8_tras_reg<1>
	# state_tras<1> & state_tras<3> & !state_tras<0> & 
	key_entry2 & !txd_buf<0>
;Imported pterms FB7_14
	# key_entry2 & !txd_buf<0> & !div8_tras_reg<2>
	# !key_entry2 & !txd_buf<0> & !key_entry1
	# state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<0>
	# !state_tras<2> & state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<0>
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & key_entry2 & !txd_buf<0>
;Imported pterms FB7_13
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & !send_state<2> & 
	send_state<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB7_16
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	div8_tras_reg<0> & !txd_buf<1> & div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & div8_tras_reg<0> & !txd_buf<1> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>;
   txd_buf<0>.CLK = clkbaud8x;
   txd_buf<0>.AR = !rst;

MACROCELL | 5 | 15 | state_rec<0>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 24 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 5 | 5 | 6 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16
INPUTS | 11 | state_rec<0>  | state_rec<1>  | state_rec<2>  | state_rec<3>  | recstart_tmp  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst  | lowbit_OBUF$BUF3.EXP
INPUTMC | 10 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 5 | 2 | 3 | 5 | 13 | 5 | 12 | 1 | 13 | 5 | 14
INPUTP | 1 | 79
IMPORTS | 1 | 5 | 14
EQ | 13 | 
   state_rec<0>.T = !state_rec<0> & !state_rec<1> & !state_rec<2> & 
	!state_rec<3> & recstart_tmp
	# state_rec<2> & !state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !state_rec<1> & !state_rec<2> & state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2>
;Imported pterms FB6_15
	# state_rec<0> & !state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# state_rec<1> & !state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   state_rec<0>.CLK = clkbaud8x;
   state_rec<0>.AR = !rst;

MACROCELL | 5 | 2 | state_rec<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 24 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 0 | 5 | 4 | 5 | 5 | 5 | 6 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16 | 5 | 1
INPUTS | 15 | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst  | rxd_buf<2>  | rxd_buf<0>  | rxd_buf<4>  | rxd_buf<5>  | rxd_buf<6>  | rxd_buf<3>  | rxd_buf<7>  | rxd_buf<1>
INPUTMC | 14 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 1 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17 | 3 | 13
INPUTP | 1 | 79
EXPORTS | 1 | 5 | 1
EQ | 9 | 
   state_rec<1>.T = state_rec<0> & !state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   state_rec<1>.CLK = clkbaud8x;
   state_rec<1>.AR = !rst;
    state_rec<1>.EXP  =  !rxd_buf<2> & !rxd_buf<0> & rxd_buf<4> & 
	rxd_buf<5> & !rxd_buf<6> & !rxd_buf<3> & !rxd_buf<7>
	# rxd_buf<1> & rxd_buf<2> & !rxd_buf<0> & 
	!rxd_buf<4> & !rxd_buf<5> & rxd_buf<6> & !rxd_buf<3> & 
	!rxd_buf<7>

MACROCELL | 5 | 0 | state_rec<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 21 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 5 | 3 | 3 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 4 | 5 | 5 | 5 | 6 | 3 | 2 | 3 | 4 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 0 | 5 | 16
INPUTS | 11 | state_rec<0>  | state_rec<1>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst  | rxd_buf<7>  | state_rec<2>  | rxd_reg2
INPUTMC | 10 | 5 | 15 | 5 | 2 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 1 | 13 | 5 | 17 | 5 | 0 | 2 | 6
INPUTP | 1 | 79
EXPORTS | 1 | 5 | 17
EQ | 7 | 
   state_rec<2>.T = state_rec<0> & state_rec<1> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2>;
   state_rec<2>.CLK = clkbaud8x;
   state_rec<2>.AR = !rst;
    state_rec<2>.EXP  =  !rxd_buf<7> & !state_rec<0> & !state_rec<1> & 
	!state_rec<2> & state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2> & rxd_reg2

MACROCELL | 6 | 17 | trasstart
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 7 | 6 | 7 | 2 | 14 | 6 | 17 | 2 | 2 | 2 | 12 | 2 | 11 | 6 | 16
INPUTS | 11 | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | send_state<1>  | trasstart  | send_state<2>  | EXP30_.EXP  | clkbaud8x  | rst  | key_entry2
INPUTMC | 10 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 1 | 15 | 6 | 17 | 1 | 14 | 6 | 16 | 1 | 13 | 2 | 10
INPUTP | 1 | 79
IMPORTS | 1 | 6 | 16
EQ | 22 | 
   trasstart.T = !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & !send_state<1> & !trasstart
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & !send_state<2> & !trasstart
;Imported pterms FB7_17
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & !send_state<0> & !trasstart
	# state_tras<2> & !state_tras<1> & state_tras<3> & 
	!trasstart & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<2> & state_tras<3> & !state_tras<0> & 
	!trasstart & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<2> & state_tras<1> & state_tras<3> & 
	!trasstart & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & trasstart & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;
   trasstart.CLK = clkbaud8x;
   trasstart.AR = !rst;
   trasstart.CE = key_entry2;

MACROCELL | 5 | 4 | state_rec<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 25 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 5 | 5 | 5 | 6 | 3 | 2 | 3 | 3 | 3 | 5 | 3 | 8 | 3 | 10 | 3 | 12 | 3 | 14 | 3 | 16 | 5 | 14 | 5 | 16 | 5 | 3
INPUTS | 17 | state_rec<0>  | state_rec<1>  | state_rec<2>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | clkbaud8x  | rst  | rxd_buf<1>  | rxd_buf<2>  | rxd_buf<0>  | rxd_buf<4>  | rxd_buf<5>  | rxd_buf<6>  | rxd_buf<3>  | rxd_buf<7>
INPUTMC | 16 | 5 | 15 | 5 | 2 | 5 | 0 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 1 | 13 | 3 | 13 | 3 | 17 | 3 | 15 | 3 | 7 | 3 | 6 | 3 | 4 | 3 | 9 | 5 | 17
INPUTP | 1 | 79
EXPORTS | 1 | 5 | 3
EQ | 11 | 
   state_rec<3>.T = state_rec<0> & state_rec<1> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# state_rec<0> & !state_rec<1> & !state_rec<2> & 
	state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>;
   state_rec<3>.CLK = clkbaud8x;
   state_rec<3>.AR = !rst;
    state_rec<3>.EXP  =  !rxd_buf<1> & !rxd_buf<2> & rxd_buf<0> & 
	!rxd_buf<4> & !rxd_buf<5> & rxd_buf<6> & !rxd_buf<3> & 
	!rxd_buf<7>

MACROCELL | 6 | 12 | txd_buf<2>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 7 | 6 | 12 | 6 | 2 | 6 | 0 | 6 | 1 | 6 | 10 | 6 | 11 | 6 | 13
INPUTS | 15 | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | txd_buf<2>  | div8_tras_reg<0>  | state_tras<2>  | send_state<1>  | send_state<2>  | send_state<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | EXP27_.EXP  | clkbaud8x  | rst
INPUTMC | 14 | 2 | 9 | 2 | 4 | 2 | 15 | 2 | 10 | 6 | 12 | 2 | 2 | 2 | 5 | 1 | 15 | 1 | 14 | 1 | 0 | 2 | 12 | 2 | 11 | 6 | 11 | 1 | 13
INPUTP | 1 | 79
EXPORTS | 1 | 6 | 13
IMPORTS | 1 | 6 | 11
EQ | 39 | 
   !txd_buf<2>.D = key_entry2 & !txd_buf<2> & !div8_tras_reg<0>
	# state_tras<1> & state_tras<3> & !state_tras<0> & 
	key_entry2 & !txd_buf<2>
;Imported pterms FB7_12
	# key_entry2 & !txd_buf<2> & !div8_tras_reg<1>
	# key_entry2 & !txd_buf<2> & !div8_tras_reg<2>
	# !key_entry2 & !txd_buf<2> & !key_entry1
	# state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<2>
	# !state_tras<2> & state_tras<1> & state_tras<3> & 
	key_entry2 & !txd_buf<2>
;Imported pterms FB7_11
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & key_entry2 & !txd_buf<2>
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	!txd_buf<3> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	!txd_buf<3> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	!txd_buf<3> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & !txd_buf<3> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB7_10
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & !send_state<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>;
   txd_buf<2>.CLK = clkbaud8x;
   txd_buf<2>.AR = !rst;
    txd_buf<2>.EXP  =  state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & !send_state<2> & 
	send_state<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>

MACROCELL | 6 | 6 | txd_buf<3>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 5 | 6 | 10 | 6 | 6 | 6 | 4 | 6 | 5 | 6 | 7
INPUTS | 17 | key_entry2  | txd_buf<3>  | div8_tras_reg<0>  | state_tras<2>  | state_tras<1>  | state_tras<3>  | txd_buf<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | txd  | state_tras<0>  | send_state<1>  | send_state<2>  | send_state<0>  | clkbaud8x  | rst  | EXP23_.EXP
INPUTMC | 16 | 2 | 10 | 6 | 6 | 2 | 2 | 2 | 5 | 2 | 9 | 2 | 4 | 6 | 14 | 2 | 12 | 2 | 11 | 6 | 9 | 2 | 15 | 1 | 15 | 1 | 14 | 1 | 0 | 1 | 13 | 6 | 5
INPUTP | 1 | 79
EXPORTS | 1 | 6 | 7
IMPORTS | 1 | 6 | 5
EQ | 42 | 
   txd_buf<3>.D = key_entry2 & txd_buf<3> & !div8_tras_reg<0>
;Imported pterms FB7_6
	# key_entry2 & txd_buf<3> & !div8_tras_reg<1>
	# key_entry2 & txd_buf<3> & !div8_tras_reg<2>
	# !key_entry2 & txd_buf<3> & !key_entry1
	# state_tras<2> & !state_tras<1> & state_tras<3> & 
	key_entry2 & txd_buf<3>
	# !state_tras<2> & state_tras<1> & state_tras<3> & 
	key_entry2 & txd_buf<3>
;Imported pterms FB7_5
	# state_tras<2> & state_tras<3> & !state_tras<0> & 
	key_entry2 & txd_buf<3>
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<3>
	# state_tras<2> & !state_tras<3> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# !state_tras<3> & state_tras<0> & key_entry2 & 
	txd_buf<4> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB7_4
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & txd_buf<4> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<2> & send_state<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & send_state<2> & 
	!send_state<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;
   txd_buf<3>.CLK = clkbaud8x;
   txd_buf<3>.AR = !rst;
    txd_buf<3>.EXP  =  !state_tras<2> & !state_tras<1> & state_tras<3> & 
	txd_buf<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# txd & !state_tras<2> & !state_tras<1> &
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