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📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
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	!state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	send_state<0>;
   key_entry2.CLK = clkbaud8x;
   key_entry2.AR = !rst;
    key_entry2.EXP  =  state_tras<0> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>

MACROCELL | 3 | 7 | rxd_buf<4>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 18 | 3 | 7 | 3 | 9 | 5 | 7 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 6 | 3 | 8 | 3 | 10 | 5 | 2 | 5 | 4 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 13 | rxd_buf<4>  | rxd_buf<5>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | rxd_buf<5>.EXP  | lowbit_OBUF$BUF6.EXP
INPUTMC | 12 | 3 | 7 | 3 | 6 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 5 | 2 | 5 | 0 | 1 | 13 | 3 | 6 | 3 | 8
INPUTP | 1 | 79
IMPORTS | 2 | 3 | 6 | 3 | 8
EQ | 28 | 
   rxd_buf<4>.T = rxd_buf<4> & !rxd_buf<5> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<5> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<5> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_7
	# !rxd_buf<4> & rxd_buf<5> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_9
	# !rxd_buf<4> & rxd_buf<5> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<4> & rxd_buf<5> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<5> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !rxd_buf<4> & rxd_buf<5> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<4>.CLK = clkbaud8x;
   rxd_buf<4>.AR = !rst;

MACROCELL | 3 | 6 | rxd_buf<5>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 18 | 3 | 7 | 3 | 6 | 5 | 7 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 4 | 3 | 5 | 3 | 8 | 5 | 2 | 5 | 4 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 12 | rxd_buf<5>  | rxd_buf<6>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | rxd_buf<4>  | clkbaud8x  | rst  | EXP15_.EXP
INPUTMC | 11 | 3 | 6 | 3 | 4 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 5 | 2 | 3 | 7 | 1 | 13 | 3 | 5
INPUTP | 1 | 79
EXPORTS | 1 | 3 | 7
IMPORTS | 1 | 3 | 5
EQ | 31 | 
   rxd_buf<5>.T = rxd_buf<5> & !rxd_buf<6> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<5> & !rxd_buf<6> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_6
	# rxd_buf<5> & !rxd_buf<6> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<5> & rxd_buf<6> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<5> & rxd_buf<6> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<5> & rxd_buf<6> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<5> & !rxd_buf<6> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
;Imported pterms FB4_5
	# !rxd_buf<5> & rxd_buf<6> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<5>.CLK = clkbaud8x;
   rxd_buf<5>.AR = !rst;
    rxd_buf<5>.EXP  =  !rxd_buf<4> & rxd_buf<5> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>

MACROCELL | 3 | 4 | rxd_buf<6>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 18 | 3 | 6 | 3 | 4 | 5 | 7 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 2 | 3 | 3 | 3 | 5 | 5 | 2 | 5 | 4 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 13 | rxd_buf<6>  | rxd_buf<7>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | rxd_buf<5>  | clkbaud8x  | rst  | state_rec<2>  | EXP14_.EXP
INPUTMC | 12 | 3 | 4 | 5 | 17 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 5 | 2 | 3 | 6 | 1 | 13 | 5 | 0 | 3 | 3
INPUTP | 1 | 79
EXPORTS | 1 | 3 | 5
IMPORTS | 1 | 3 | 3
EQ | 31 | 
   rxd_buf<6>.T = rxd_buf<6> & !rxd_buf<7> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<6> & !rxd_buf<7> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_4
	# rxd_buf<6> & !rxd_buf<7> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<6> & rxd_buf<7> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<6> & rxd_buf<7> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<6> & rxd_buf<7> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<6> & !rxd_buf<7> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
;Imported pterms FB4_3
	# !rxd_buf<6> & rxd_buf<7> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<6>.CLK = clkbaud8x;
   rxd_buf<6>.AR = !rst;
    rxd_buf<6>.EXP  =  !rxd_buf<5> & rxd_buf<6> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>

MACROCELL | 3 | 9 | rxd_buf<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 17 | 3 | 17 | 3 | 9 | 5 | 7 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 10 | 3 | 16 | 5 | 2 | 5 | 4 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 12 | rxd_buf<4>  | rxd_buf<3>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | lowbit_OBUF$BUF7.EXP
INPUTMC | 11 | 3 | 7 | 3 | 9 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 5 | 2 | 5 | 0 | 1 | 13 | 3 | 10
INPUTP | 1 | 79
IMPORTS | 1 | 3 | 10
EQ | 27 | 
   rxd_buf<3>.T = !rxd_buf<4> & rxd_buf<3> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<4> & rxd_buf<3> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<4> & rxd_buf<3> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_11
	# rxd_buf<4> & !rxd_buf<3> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<3> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<3> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<4> & !rxd_buf<3> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !rxd_buf<4> & rxd_buf<3> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<3>.CLK = clkbaud8x;
   rxd_buf<3>.AR = !rst;

MACROCELL | 1 | 15 | send_state<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 6 | 6 | 2 | 14 | 2 | 10 | 1 | 14 | 6 | 12 | 6 | 17 | 6 | 9 | 6 | 3 | 6 | 1 | 2 | 16 | 2 | 8 | 2 | 9 | 2 | 15 | 6 | 0 | 6 | 15
INPUTS | 11 | send_state<0>  | clkbaud8x  | rst  | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>
INPUTMC | 10 | 1 | 0 | 1 | 13 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 2 | 10 | 2 | 2 | 2 | 12 | 2 | 11
INPUTP | 1 | 79
EQ | 6 | 
   send_state<1>.T = send_state<0>;
   send_state<1>.CLK = clkbaud8x;
   send_state<1>.AR = !rst;
   send_state<1>.CE = state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;

MACROCELL | 1 | 14 | send_state<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 13 | 6 | 6 | 2 | 14 | 2 | 10 | 6 | 12 | 6 | 17 | 6 | 9 | 6 | 3 | 6 | 0 | 2 | 16 | 2 | 8 | 2 | 9 | 2 | 15 | 6 | 15
INPUTS | 12 | send_state<1>  | send_state<0>  | clkbaud8x  | rst  | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>
INPUTMC | 11 | 1 | 15 | 1 | 0 | 1 | 13 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 2 | 10 | 2 | 2 | 2 | 12 | 2 | 11
INPUTP | 1 | 79
EQ | 6 | 
   send_state<2>.T = send_state<1> & send_state<0>;
   send_state<2>.CLK = clkbaud8x;
   send_state<2>.AR = !rst;
   send_state<2>.CE = state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;

MACROCELL | 5 | 17 | rxd_buf<7>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 19 | 3 | 4 | 5 | 17 | 5 | 7 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 2 | 3 | 3 | 5 | 0 | 5 | 2 | 5 | 4 | 5 | 6 | 5 | 10 | 5 | 16 | 7 | 14
INPUTS | 13 | rxd_buf<7>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | rxd_reg2  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | state_rec<2>.EXP  | lowbit_OBUF$BUF2.EXP
INPUTMC | 12 | 5 | 17 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 2 | 6 | 5 | 2 | 5 | 0 | 1 | 13 | 5 | 0 | 5 | 16
INPUTP | 1 | 79
IMPORTS | 2 | 5 | 0 | 5 | 16
EQ | 22 | 
   rxd_buf<7>.T = rxd_buf<7> & state_rec<0> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & !rxd_reg2
	# rxd_buf<7> & state_rec<1> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & !rxd_reg2
	# rxd_buf<7> & state_rec<2> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & !rxd_reg2
;Imported pterms FB6_1
	# !rxd_buf<7> & !state_rec<0> & !state_rec<1> & 
	!state_rec<2> & state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2> & rxd_reg2
;Imported pterms FB6_17
	# !rxd_buf<7> & state_rec<0> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & rxd_reg2
	# !rxd_buf<7> & state_rec<1> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & rxd_reg2
	# !rxd_buf<7> & state_rec<2> & !state_rec<3> & 
	div8_rec_reg<0> & div8_rec_reg<1> & div8_rec_reg<2> & rxd_reg2
	# rxd_buf<7> & !state_rec<0> & !state_rec<1> & 
	!state_rec<2> & state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2> & !rxd_reg2;
   rxd_buf<7>.CLK = clkbaud8x;
   rxd_buf<7>.AR = !rst;

MACROCELL | 1 | 0 | send_state<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 9 | 6 | 6 | 2 | 14 | 2 | 10 | 1 | 15 | 1 | 14 | 6 | 12 | 6 | 16 | 6 | 9 | 6 | 3
INPUTS | 10 | clkbaud8x  | rst  | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>
INPUTMC | 9 | 1 | 13 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 2 | 10 | 2 | 2 | 2 | 12 | 2 | 11
INPUTP | 1 | 79
EQ | 6 | 
   send_state<0>.T = Vcc;
   send_state<0>.CLK = clkbaud8x;
   send_state<0>.AR = !rst;
   send_state<0>.CE = state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>;

MACROCELL | 6 | 14 | txd_buf<0>
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 5 | 6 | 8 | 6 | 14 | 6 | 6 | 6 | 7 | 6 | 13
INPUTS | 11 | state_tras<1>  | state_tras<3>  | state_tras<0>  | key_entry2  | txd_buf<0>  | div8_tras_reg<0>  | div8_tras_reg<1>  | EXP28_.EXP  | EXP29_.EXP  | clkbaud8x  | rst
INPUTMC | 10 | 2 | 9 | 2 | 4 | 2 | 15 | 2 | 10 | 6 | 14 | 2 | 2 | 2 | 12 | 6 | 13 | 6 | 15 | 1 | 13
INPUTP | 1 | 79
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