serial.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

MDF Database:  version 1.0
MDF_INFO | serial | XC95144XL-10-TQ144
MACROCELL | 6 | 9 | txd_reg
ATTRIBUTES | 8782818 | 0
OUTPUTMC | 4 | 6 | 8 | 6 | 6 | 6 | 7 | 6 | 10
INPUTS | 14 | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | send_state<1>  | send_state<2>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | send_state<0>  | EXP25_.EXP  | clkbaud8x  | rst  | key_entry2
INPUTMC | 13 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 1 | 15 | 1 | 14 | 2 | 2 | 2 | 12 | 2 | 11 | 1 | 0 | 6 | 8 | 1 | 13 | 2 | 10
INPUTP | 1 | 79
EXPORTS | 1 | 6 | 10
IMPORTS | 1 | 6 | 8
EQ | 34 | 
   txd.D = ;Imported pterms FB7_9
	  txd & !div8_tras_reg<0>
	# txd & !div8_tras_reg<1>
	# txd & !div8_tras_reg<2>
	# txd & state_tras<2> & state_tras<3>
	# !state_tras<3> & state_tras<0> & txd_buf<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
;Imported pterms FB7_8
	# txd & state_tras<1> & state_tras<3>
	# txd & !state_tras<2> & !state_tras<1> & 
	!state_tras<3> & !state_tras<0> & !trasstart
	# state_tras<2> & !state_tras<3> & txd_buf<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<1> & !state_tras<3> & txd_buf<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	state_tras<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
;Imported pterms FB7_7
	# !state_tras<2> & !state_tras<1> & state_tras<3> & 
	txd_buf<0> & div8_tras_reg<0> & div8_tras_reg<1> & 
	div8_tras_reg<2>
	# txd & !state_tras<2> & !state_tras<1> & 
	!state_tras<3> & !state_tras<0> & send_state<1> & send_state<2> & 
	send_state<0>;
   txd.CLK = clkbaud8x;
   txd.AP = !rst;
   txd.CE = key_entry2;
    txd_reg.EXP  =  state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & !send_state<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>

MACROCELL | 2 | 5 | state_tras<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 33 | 6 | 8 | 2 | 4 | 2 | 14 | 2 | 10 | 1 | 15 | 1 | 14 | 1 | 0 | 6 | 13 | 6 | 17 | 6 | 11 | 6 | 5 | 2 | 1 | 6 | 2 | 2 | 7 | 2 | 17 | 2 | 0 | 2 | 2 | 2 | 6 | 2 | 8 | 2 | 9 | 2 | 15 | 2 | 16 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 6 | 6 | 7 | 6 | 9 | 6 | 10 | 6 | 12 | 6 | 15 | 6 | 16
INPUTS | 9 | state_tras<1>  | state_tras<0>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | clkbaud8x  | rst  | key_entry2  | rxd_reg1
INPUTMC | 8 | 2 | 9 | 2 | 15 | 2 | 2 | 2 | 12 | 2 | 11 | 1 | 13 | 2 | 10 | 2 | 13
INPUTP | 1 | 79
EXPORTS | 1 | 2 | 6
EQ | 6 | 
   state_tras<2>.T = state_tras<1> & state_tras<0> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>;
   state_tras<2>.CLK = clkbaud8x;
   state_tras<2>.AR = !rst;
   state_tras<2>.CE = key_entry2;
    state_tras<2>.EXP  =  rxd_reg1

MACROCELL | 2 | 9 | state_tras<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 34 | 6 | 7 | 2 | 5 | 2 | 4 | 2 | 14 | 2 | 10 | 1 | 15 | 1 | 14 | 1 | 0 | 6 | 14 | 6 | 17 | 6 | 12 | 6 | 5 | 2 | 1 | 6 | 2 | 2 | 7 | 2 | 16 | 2 | 0 | 2 | 2 | 2 | 6 | 2 | 8 | 2 | 9 | 2 | 15 | 2 | 17 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 6 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 13 | 6 | 15 | 6 | 16
INPUTS | 15 | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | clkbaud8x  | rst  | key_entry2  | div8_tras_reg<0>  | txd_buf<5>  | div8_tras_reg<1>  | div8_tras_reg<2>  | txd_buf<6>  | send_state<1>  | send_state<2>  | key_entry2.EXP
INPUTMC | 14 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 1 | 13 | 2 | 10 | 2 | 2 | 2 | 7 | 2 | 12 | 2 | 11 | 2 | 17 | 1 | 15 | 1 | 14 | 2 | 10
INPUTP | 1 | 79
EXPORTS | 1 | 2 | 8
IMPORTS | 1 | 2 | 10
EQ | 12 | 
   state_tras<1>.T = ;Imported pterms FB3_11
	  state_tras<0> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2>;
   state_tras<1>.CLK = clkbaud8x;
   state_tras<1>.AR = !rst;
   state_tras<1>.CE = key_entry2;
    state_tras<1>.EXP  =  !state_tras<2> & !state_tras<1> & state_tras<3> & 
	!state_tras<0> & key_entry2 & div8_tras_reg<0> & !txd_buf<5> & 
	div8_tras_reg<1> & div8_tras_reg<2> & txd_buf<6>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & send_state<1> & send_state<2> & 
	div8_tras_reg<0> & txd_buf<5> & div8_tras_reg<1> & div8_tras_reg<2>

MACROCELL | 2 | 4 | state_tras<3>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 33 | 6 | 8 | 2 | 14 | 2 | 10 | 1 | 15 | 1 | 14 | 1 | 0 | 6 | 14 | 6 | 17 | 6 | 12 | 6 | 5 | 2 | 1 | 6 | 2 | 2 | 7 | 2 | 17 | 2 | 0 | 2 | 2 | 2 | 6 | 2 | 8 | 2 | 9 | 2 | 15 | 2 | 16 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 6 | 6 | 7 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 13 | 6 | 15 | 6 | 16
INPUTS | 9 | state_tras<2>  | state_tras<1>  | state_tras<0>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | clkbaud8x  | rst  | key_entry2
INPUTMC | 8 | 2 | 5 | 2 | 9 | 2 | 15 | 2 | 2 | 2 | 12 | 2 | 11 | 1 | 13 | 2 | 10
INPUTP | 1 | 79
EQ | 5 | 
   state_tras<3>.T = state_tras<2> & state_tras<1> & state_tras<0> & 
	div8_tras_reg<0> & div8_tras_reg<1> & div8_tras_reg<2>;
   state_tras<3>.CLK = clkbaud8x;
   state_tras<3>.AR = !rst;
   state_tras<3>.CE = key_entry2;

MACROCELL | 2 | 15 | state_tras<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 31 | 6 | 8 | 2 | 5 | 2 | 8 | 2 | 4 | 2 | 14 | 2 | 10 | 1 | 15 | 1 | 14 | 1 | 0 | 6 | 14 | 6 | 17 | 6 | 12 | 6 | 4 | 2 | 0 | 6 | 2 | 2 | 6 | 2 | 16 | 2 | 2 | 2 | 9 | 2 | 15 | 2 | 17 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 6 | 6 | 7 | 6 | 9 | 6 | 10 | 6 | 13 | 6 | 15 | 6 | 16
INPUTS | 14 | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | send_state<1>  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>  | txd_buf<6>  | send_state<2>  | EXP12_.EXP  | clkbaud8x  | rst  | key_entry2
INPUTMC | 13 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 1 | 15 | 2 | 2 | 2 | 12 | 2 | 11 | 2 | 17 | 1 | 14 | 2 | 14 | 1 | 13 | 2 | 10
INPUTP | 1 | 79
EXPORTS | 1 | 2 | 16
IMPORTS | 1 | 2 | 14
EQ | 17 | 
   !state_tras<0>.T = ;Imported pterms FB3_15
	  !div8_tras_reg<0>
	# !div8_tras_reg<1>
	# !div8_tras_reg<2>
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & !trasstart
	# !state_tras<2> & !state_tras<1> & !state_tras<3> & 
	!state_tras<0> & send_state<1> & send_state<2> & send_state<0>;
   state_tras<0>.CLK = clkbaud8x;
   state_tras<0>.AR = !rst;
   state_tras<0>.CE = key_entry2;
    state_tras<0>.EXP  =  state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<1> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2> & !txd_buf<6>
	# state_tras<2> & state_tras<1> & state_tras<3> & 
	state_tras<0> & key_entry2 & !send_state<2> & div8_tras_reg<0> & 
	div8_tras_reg<1> & div8_tras_reg<2> & !txd_buf<6>

MACROCELL | 3 | 13 | rxd_buf<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 17 | 3 | 13 | 3 | 15 | 5 | 7 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 12 | 3 | 14 | 5 | 2 | 5 | 4 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 12 | rxd_buf<1>  | rxd_buf<2>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | EXP16_.EXP
INPUTMC | 11 | 3 | 13 | 3 | 17 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 5 | 2 | 5 | 0 | 1 | 13 | 3 | 12
INPUTP | 1 | 79
IMPORTS | 1 | 3 | 12
EQ | 27 | 
   rxd_buf<1>.T = rxd_buf<1> & !rxd_buf<2> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<2> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<2> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_13
	# !rxd_buf<1> & rxd_buf<2> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<2> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<2> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<2> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<2> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<1>.CLK = clkbaud8x;
   rxd_buf<1>.AR = !rst;

MACROCELL | 3 | 17 | rxd_buf<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 17 | 3 | 13 | 3 | 17 | 5 | 7 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 1 | 3 | 12 | 3 | 16 | 5 | 2 | 5 | 4 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 12 | rxd_buf<2>  | rxd_buf<3>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | EXP18_.EXP
INPUTMC | 11 | 3 | 17 | 3 | 9 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 5 | 2 | 5 | 0 | 1 | 13 | 3 | 16
INPUTP | 1 | 79
IMPORTS | 1 | 3 | 16
EQ | 27 | 
   rxd_buf<2>.T = rxd_buf<2> & !rxd_buf<3> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<2> & !rxd_buf<3> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<2> & !rxd_buf<3> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_17
	# !rxd_buf<2> & rxd_buf<3> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<2> & rxd_buf<3> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<2> & rxd_buf<3> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<2> & !rxd_buf<3> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !rxd_buf<2> & rxd_buf<3> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<2>.CLK = clkbaud8x;
   rxd_buf<2>.AR = !rst;

MACROCELL | 3 | 15 | rxd_buf<0>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 14 | 3 | 15 | 5 | 7 | 3 | 0 | 5 | 8 | 5 | 9 | 5 | 3 | 7 | 15 | 5 | 1 | 3 | 14 | 5 | 2 | 5 | 4 | 5 | 6 | 5 | 10 | 7 | 14
INPUTS | 12 | rxd_buf<1>  | rxd_buf<0>  | state_rec<0>  | state_rec<3>  | div8_rec_reg<0>  | div8_rec_reg<1>  | div8_rec_reg<2>  | state_rec<1>  | state_rec<2>  | clkbaud8x  | rst  | EXP17_.EXP
INPUTMC | 11 | 3 | 13 | 3 | 15 | 5 | 15 | 5 | 4 | 2 | 3 | 5 | 13 | 5 | 12 | 5 | 2 | 5 | 0 | 1 | 13 | 3 | 14
INPUTP | 1 | 79
IMPORTS | 1 | 3 | 14
EQ | 27 | 
   rxd_buf<0>.T = !rxd_buf<1> & rxd_buf<0> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<0> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<0> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
;Imported pterms FB4_15
	# rxd_buf<1> & !rxd_buf<0> & state_rec<0> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<0> & state_rec<1> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<0> & state_rec<2> & 
	!state_rec<3> & div8_rec_reg<0> & div8_rec_reg<1> & 
	div8_rec_reg<2>
	# rxd_buf<1> & !rxd_buf<0> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>
	# !rxd_buf<1> & rxd_buf<0> & !state_rec<0> & 
	!state_rec<1> & !state_rec<2> & state_rec<3> & div8_rec_reg<0> & 
	div8_rec_reg<1> & div8_rec_reg<2>;
   rxd_buf<0>.CLK = clkbaud8x;
   rxd_buf<0>.AR = !rst;

MACROCELL | 2 | 10 | key_entry2
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 32 | 6 | 9 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 2 | 10 | 1 | 15 | 1 | 14 | 1 | 0 | 6 | 14 | 6 | 17 | 6 | 12 | 6 | 6 | 2 | 1 | 6 | 2 | 2 | 7 | 2 | 17 | 0 | 8 | 2 | 0 | 2 | 2 | 2 | 6 | 2 | 8 | 2 | 16 | 6 | 0 | 6 | 1 | 6 | 3 | 6 | 4 | 6 | 5 | 6 | 10 | 6 | 11 | 6 | 13 | 6 | 15
INPUTS | 14 | key_entry2  | key_entry1  | state_tras<2>  | state_tras<1>  | state_tras<3>  | state_tras<0>  | send_state<1>  | send_state<2>  | send_state<0>  | clkbaud8x  | rst  | div8_tras_reg<0>  | div8_tras_reg<1>  | div8_tras_reg<2>
INPUTMC | 13 | 2 | 10 | 0 | 8 | 2 | 5 | 2 | 9 | 2 | 4 | 2 | 15 | 1 | 15 | 1 | 14 | 1 | 0 | 1 | 13 | 2 | 2 | 2 | 12 | 2 | 11
INPUTP | 1 | 79
EXPORTS | 1 | 2 | 9
EQ | 8 | 
   key_entry2.T = !key_entry2 & key_entry1
	# !state_tras<2> & !state_tras<1> & !state_tras<3> &