lcd1602.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

#      LUT2_L                      : 2
#      LUT3                        : 14
#      LUT3_L                      : 1
#      LUT4                        : 19
#      LUT4_D                      : 4
#      LUT4_L                      : 1
#      MUXCY                       : 20
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 20
# FlipFlops/Latches                : 59
#      FDC                         : 10
#      FDCE                        : 7
#      FDE                         : 16
#      FDP                         : 1
#      FDR                         : 18
#      FDR_1                       : 1
#      LD                          : 6
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 3
#      OBUFT                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      50  out of    768     6%  
 Number of Slice Flip Flops:            59  out of   1536     3%  
 Number of 4 input LUTs:                69  out of   1536     4%  
 Number of bonded IOBs:                 13  out of     96    13%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clk                                | BUFGP                          | 4     |
XLXI_1/count_3:Q                   | NONE                           | 16    |
XLXI_2/clk_int:Q                   | BUFG                           | 30    |
N32(XLXI_2/state_FFd6-In1:O)       | NONE(*)(XLXI_2/ddram_1_ddram_0)| 5     |
XLXI_2/tc_clkcnt(XLXI_2/_n003867:O)| NONE(*)(XLXI_2/clkdiv)         | 1     |
XLXI_2/clkdiv:Q                    | NONE                           | 2     |
XLXI_2/state_FFd6-In1:LO           | NONE                           | 1     |
-----------------------------------+--------------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 10.071ns (Maximum Frequency: 99.295MHz)
   Minimum input arrival time before clock: 6.550ns
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 4.953ns (frequency: 201.898MHz)
  Total number of paths / destination ports: 10 / 4
-------------------------------------------------------------------------
Delay:               4.953ns (Levels of Logic = 1)
  Source:            XLXI_1/count_3 (FF)
  Destination:       XLXI_1/count_3 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_1/count_3 to XLXI_1/count_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             17   1.085   2.610  XLXI_1/count_3 (XLXI_1/count_3)
     LUT4:I1->O            1   0.549   0.000  lcd1602_XLXI_1/count__n0000<3>_xor11 (XLXI_1/count__n0000<3>)
     FDC:D                     0.709          XLXI_1/count_3
    ----------------------------------------
    Total                      4.953ns (2.343ns logic, 2.610ns route)
                                       (47.3% logic, 52.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_1/count_3:Q'
  Clock period: 8.327ns (frequency: 120.091MHz)
  Total number of paths / destination ports: 392 / 32
-------------------------------------------------------------------------
Delay:               8.327ns (Levels of Logic = 3)
  Source:            XLXI_2/clkcnt_10 (FF)
  Destination:       XLXI_2/clkcnt_13 (FF)
  Source Clock:      XLXI_1/count_3:Q rising
  Destination Clock: XLXI_1/count_3:Q rising

  Data Path: XLXI_2/clkcnt_10 to XLXI_2/clkcnt_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.085   1.206  XLXI_2/clkcnt_10 (XLXI_2/clkcnt_10)
     LUT4:I0->O            1   0.549   1.035  XLXI_2/_n00388 (CHOICE374)
     LUT4_D:I0->LO         1   0.549   0.100  XLXI_2/_n003867 (N110)
     LUT2:I1->O           16   0.549   2.520  XLXI_2/_n00111 (XLXI_2/_n0011)
     FDR:R                     0.734          XLXI_2/clkcnt_0
    ----------------------------------------
    Total                      8.327ns (3.466ns logic, 4.861ns route)
                                       (41.6% logic, 58.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_2/clk_int:Q'
  Clock period: 10.071ns (frequency: 99.295MHz)
  Total number of paths / destination ports: 284 / 51
-------------------------------------------------------------------------
Delay:               10.071ns (Levels of Logic = 3)
  Source:            XLXI_2/address_4 (FF)
  Destination:       XLXI_2/Mtridata_data<6> (FF)
  Source Clock:      XLXI_2/clk_int:Q rising
  Destination Clock: XLXI_2/clk_int:Q rising

  Data Path: XLXI_2/address_4 to XLXI_2/Mtridata_data<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             9   1.085   1.908  XLXI_2/address_4 (XLXI_2/address_4)
     LUT4_D:I0->O          7   0.549   1.755  XLXI_2/_n00551 (XLXI_2/_n0055)
     LUT4_D:I3->O          1   0.549   1.035  Ker2 (N2)
     LUT2:I1->O            7   0.549   1.755  XLXI_2/_n00171 (XLXI_2/_n0017)
     FDE:CE                    0.886          XLXI_2/Mtridata_data<6>
    ----------------------------------------
    Total                     10.071ns (3.618ns logic, 6.453ns route)
                                       (35.9% logic, 64.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_2/_n003867:O'
  Clock period: 4.710ns (frequency: 212.314MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               4.710ns (Levels of Logic = 1)
  Source:            XLXI_2/clkdiv (FF)
  Destination:       XLXI_2/clkdiv (FF)
  Source Clock:      XLXI_2/_n003867:O rising
  Destination Clock: XLXI_2/_n003867:O rising

  Data Path: XLXI_2/clkdiv to XLXI_2/clkdiv
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   1.085   1.332  XLXI_2/clkdiv (XLXI_2/clkdiv)
     INV:I->O              1   0.549   1.035  XLXI_2/_n00691_INV_0 (XLXI_2/_n0069)
     FDR:D                     0.709          XLXI_2/clkdiv
    ----------------------------------------
    Total                      4.710ns (2.343ns logic, 2.367ns route)
                                       (49.7% logic, 50.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_2/clkdiv:Q'
  Clock period: 8.437ns (frequency: 118.526MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               8.437ns (Levels of Logic = 2)
  Source:            XLXI_2/clk_int (FF)
  Destination:       XLXI_2/clk_int (FF)
  Source Clock:      XLXI_2/clkdiv:Q rising
  Destination Clock: XLXI_2/clkdiv:Q rising

  Data Path: XLXI_2/clk_int to XLXI_2/clk_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   1.085   1.035  XLXI_2/clk_int (XLXI_2/clk_int1)
     BUFG:I->O            31   0.649   3.375  XLXI_2/clk_int_BUFG (XLXI_2/clk_int)
     INV:I->O              1   0.549   1.035  XLXI_2/_n00701_INV_0 (XLXI_2/_n0070)
     FDR:D                     0.709          XLXI_2/clk_int
    ----------------------------------------
    Total                      8.437ns (2.992ns logic, 5.445ns route)
                                       (35.5% logic, 64.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_1/count_3:Q'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              6.145ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       XLXI_2/clkcnt_13 (FF)
  Destination Clock: XLXI_1/count_3:Q rising

  Data Path: rst to XLXI_2/clkcnt_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  rst_IBUF (rst_IBUF)
     LUT2:I0->O           16   0.549   2.520  XLXI_2/_n00111 (XLXI_2/_n0011)
     FDR:R                     0.734          XLXI_2/clkcnt_0
    ----------------------------------------
    Total                      6.145ns (2.059ns logic, 4.086ns route)
                                       (33.5% logic, 66.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_2/clk_int:Q'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              5.622ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       XLXI_2/Mtrien_data<5> (FF)
  Destination Clock: XLXI_2/clk_int:Q rising

  Data Path: rst to XLXI_2/Mtrien_data<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  rst_IBUF (rst_IBUF)
     LUT3:I0->O            8   0.549   1.845  XLXI_2/_n00271 (XLXI_2/_n0027)
     FDE:CE                    0.886          XLXI_2/Mtrien_data<6>
    ----------------------------------------
    Total                      5.622ns (2.211ns logic, 3.411ns route)
                                       (39.3% logic, 60.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_2/_n003867:O'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.550ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       XLXI_2/clkdiv (FF)
  Destination Clock: XLXI_2/_n003867:O rising

  Data Path: rst to XLXI_2/clkdiv
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  rst_IBUF (rst_IBUF)
     INV:I->O             21   0.549   2.925  XLXI_2/lcd_e_N01_INV_0 (XLXI_2/lcd_e_N0)
     FDR:R                     0.734          XLXI_2/clkdiv
    ----------------------------------------
    Total                      6.550ns (2.059ns logic, 4.491ns route)
                                       (31.4% logic, 68.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_2/clkdiv:Q'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              6.550ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       XLXI_2/clk_int (FF)
  Destination Clock: XLXI_2/clkdiv:Q rising

  Data Path: rst to XLXI_2/clk_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  rst_IBUF (rst_IBUF)
     INV:I->O             21   0.549   2.925  XLXI_2/lcd_e_N01_INV_0 (XLXI_2/lcd_e_N0)
     FDR:R                     0.734          XLXI_2/clk_int
    ----------------------------------------
    Total                      6.550ns (2.059ns logic, 4.491ns route)
                                       (31.4% logic, 68.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2/clkdiv:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            XLXI_2/lcd_e (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      XLXI_2/clkdiv:Q falling

  Data Path: XLXI_2/lcd_e to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            2   1.085   1.206  XLXI_2/lcd_e (XLXI_2/lcd_e)
     OBUF:I->O                 4.668          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2/clk_int:Q'
  Total number of paths / destination ports: 16 / 9
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            XLXI_2/lcd_rs (FF)
  Destination:       lcd_rs (PAD)
  Source Clock:      XLXI_2/clk_int:Q rising

  Data Path: XLXI_2/lcd_rs to lcd_rs
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   1.085   1.206  XLXI_2/lcd_rs (XLXI_2/lcd_rs)
     OBUF:I->O                 4.668          lcd_rs_OBUF (lcd_rs)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 13.60 / 15.23 s | Elapsed : 14.00 / 15.00 s
 
--> 

Total memory usage is 75780 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    5 (   0 filtered)