lcd1602.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: lcd1602.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "lcd1602.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "lcd1602"
Output Format                      : NGC
Target Device                      : xc2s50-6-TQ144

---- Source Options
Top Module Name                    : lcd1602
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lcd1602.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "DIV16.v"
Module <div16> compiled
Compiling verilog file "lcd.v"
Module <lcd> compiled
Compiling verilog file "lcd1602.vf"
Module <lcd1602> compiled
No errors in compilation
Analysis of file <"lcd1602.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <lcd1602>.
Module <lcd1602> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <lcd1602>.
Analyzing module <div16>.
Module <div16> is correct for synthesis.
 
Analyzing module <lcd>.
	IDLE = <u>00000000000
	CLEAR = <u>00000000001
	RETURNCURSOR = <u>00000000010
	SETMODE = <u>00000000100
	SWITCHMODE = <u>00000001000
	SHIFT = <u>00000010000
	SETFUNCTION = <u>00000100000
	SETCGRAM = <u>00001000000
	SETDDRAM = <u>00010000000
	READFLAG = <u>00100000000
	WRITERAM = <u>01000000000
	READRAM = <u>10000000000
	cur_inc = 1
	cur_dec = 0
	cur_shift = 1
	cur_noshift = 0
	open_display = 1
	open_cur = 0
	blank_cur = 0
	shift_display = 1
	shift_cur = 0
	right_shift = 1
	left_shift = 0
	datawidth8 = 1
	datawidth4 = 0
	twoline = 1
	oneline = 0
	font5x10 = 1
	font5x7 = 0
	Calling function <ddram>.
Module <lcd> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <lcd_rw> in unit <lcd> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <lcd>.
    Related source file is "lcd.v".
INFO:Xst:1799 - State 00000000010 is never reached in FSM <state>.
INFO:Xst:1799 - State 00001000000 is never reached in FSM <state>.
INFO:Xst:1799 - State 00010000000 is never reached in FSM <state>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 9                                              |
    | Inputs             | 2                                              |
    | Outputs            | 7                                              |
    | Clock              | clk_int (rising_edge)                          |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00000000000                                    |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 8-bit latch for signal <ddram/1/ddram>.
    Found 1-bit register for signal <lcd_e>.
    Found 1-bit register for signal <lcd_rs>.
    Found 8-bit tristate buffer for signal <data>.
    Found 6-bit comparator lessequal for signal <$n0000> created at line 148.
    Found 6-bit adder for signal <$n0029> created at line 153.
    Found 6-bit comparator greater for signal <$n0055> created at line 148.
    Found 6-bit register for signal <address>.
    Found 1-bit register for signal <clk_int>.
    Found 16-bit up counter for signal <clkcnt>.
    Found 1-bit register for signal <clkdiv>.
    Found 1-bit register for signal <flag>.
    Found 1-bit register for signal <Mtridata_data<0>>.
    Found 1-bit register for signal <Mtridata_data<1>>.
    Found 1-bit register for signal <Mtridata_data<2>>.
    Found 1-bit register for signal <Mtridata_data<3>>.
    Found 1-bit register for signal <Mtridata_data<4>>.
    Found 1-bit register for signal <Mtridata_data<5>>.
    Found 1-bit register for signal <Mtridata_data<6>>.
    Found 1-bit register for signal <Mtridata_data<7>>.
    Found 1-bit register for signal <Mtrien_data<0>>.
    Found 1-bit register for signal <Mtrien_data<1>>.
    Found 1-bit register for signal <Mtrien_data<2>>.
    Found 1-bit register for signal <Mtrien_data<3>>.
    Found 1-bit register for signal <Mtrien_data<4>>.
    Found 1-bit register for signal <Mtrien_data<5>>.
    Found 1-bit register for signal <Mtrien_data<6>>.
    Found 1-bit register for signal <Mtrien_data<7>>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  27 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred   8 Tristate(s).
Unit <lcd> synthesized.


Synthesizing Unit <div16>.
    Related source file is "DIV16.v".
    Found 4-bit up counter for signal <count>.
    Summary:
	inferred   1 Counter(s).
Unit <div16> synthesized.


Synthesizing Unit <lcd1602>.
    Related source file is "lcd1602.vf".
Unit <lcd1602> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:7]> with speed1 encoding.
-------------------------
 State       | Encoding
-------------------------
 00000000000 | 1000000
 00000000001 | 0000100
 00000000010 | unreached
 00000000100 | 0001000
 00000001000 | 0000001
 00000010000 | 0010000
 00000100000 | 0100000
 00001000000 | unreached
 00010000000 | unreached
 01000000000 | 0000010
-------------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 1
 6-bit adder                       : 1
# Counters                         : 2
 16-bit up counter                 : 1
 4-bit up counter                  : 1
# Registers                        : 29
 1-bit register                    : 28
 6-bit register                    : 1
# Latches                          : 1
 8-bit latch                       : 1
# Comparators                      : 2
 6-bit comparator greater          : 1
 6-bit comparator lessequal        : 1
# Tristates                        : 8
 1-bit tristate buffer             : 8

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <lcd>: instances <Mcompar__n0055>, <Mcompar__n0000> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_1> are dual, second instance is removed
WARNING:Xst:1710 - FF/Latch  <XLXI_2/Mtridata_data<7>> (without init value) has a constant value of 0 in block <lcd1602>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2/ddram_1_ddram_7> (without init value) has a constant value of 0 in block <lcd1602>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2/ddram_1_ddram_4> (without init value) has a constant value of 0 in block <lcd1602>.

Optimizing unit <lcd1602> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcd1602, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lcd1602.ngr
Top Level Output File Name         : lcd1602
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Macro Statistics :
# Registers                        : 24
#      1-bit register              : 21
#      4-bit register              : 2
#      6-bit register              : 1
# Tristates                        : 8
#      1-bit tristate buffer       : 8
# Adders/Subtractors               : 3
#      4-bit adder                 : 2
#      6-bit adder                 : 1
# Comparators                      : 2
#      6-bit comparator greater    : 1
#      6-bit comparator lessequal  : 1

Cell Usage :
# BELS                             : 119
#      GND                         : 1
#      INV                         : 7
#      LUT1                        : 16
#      LUT1_L                      : 4
#      LUT2                        : 8