📄 lcd1602.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: lcd1602 Date: 2-21-2006, 3:47PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
66 /144 ( 46%) 277 /720 ( 38%) 125/432 ( 29%) 55 /144 ( 38%) 13 /117 ( 11%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/18 18/54 53/90 0/15
FB2 16/18 18/54 59/90 0/15
FB3 6/18 12/54 11/90 0/15
FB4 14/18 18/54 58/90 4/15
FB5 1/18 18/54 2/90 0/14
FB6 6/18 23/54 44/90 6/13
FB7 0/18 0/54 0/90 0/15
FB8 7/18 18/54 50/90 1/15
----- ----- ----- -----
66/144 125/432 277/720 11/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 13 109
Output : 11 11 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 13 13
** Power Data **
There are 66 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:828 - Signal 'XLXI_2/ddram_1_ddram<6>.RSTF' has been minimized to
'GND'.
The signal is removed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
because too many function block product terms are required. Buffering output
signal data<5> to allow all signals assigned to this function block to be
placed.
************************* Summary of Mapped Logic ************************
** 11 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
data<6> 9 12 FB4_1 118 I/O O STD FAST RESET
lcd_e 2 3 FB4_2 126 I/O O STD FAST RESET
lcd_rw 0 0 FB4_9 131 I/O O STD FAST
lcd_rs 5 10 FB4_11 132 I/O O STD FAST RESET
data<0> 9 12 FB6_2 106 I/O O STD FAST RESET
data<2> 10 12 FB6_4 111 I/O O STD FAST RESET
data<3> 9 12 FB6_8 113 I/O O STD FAST RESET
data<5> 2 2 FB6_9 116 I/O O STD FAST
data<4> 7 11 FB6_10 115 I/O O STD FAST RESET
data<7> 7 10 FB6_11 119 I/O O STD FAST RESET
data<1> 10 12 FB8_16 107 I/O O STD FAST RESET
** 55 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXI_2/clkcnt<9> 3 12 FB1_3 STD RESET
XLXI_2/clkcnt<8> 3 11 FB1_4 STD RESET
XLXI_2/clkcnt<7> 3 10 FB1_5 STD RESET
XLXI_2/clkcnt<5> 3 8 FB1_6 STD RESET
XLXI_2/clkcnt<4> 3 7 FB1_7 STD RESET
XLXI_2/clkcnt<3> 3 6 FB1_8 STD RESET
XLXI_2/clkcnt<2> 3 5 FB1_9 STD RESET
XLXI_2/clkcnt<1> 3 4 FB1_10 STD RESET
XLXI_2/clkcnt<14> 3 17 FB1_11 STD RESET
XLXI_2/clkcnt<13> 3 16 FB1_12 STD RESET
XLXI_2/clkcnt<0> 3 18 FB1_13 STD RESET
XLXI_2/clkcnt<6> 4 18 FB1_14 STD RESET
XLXI_2/clkcnt<15> 4 18 FB1_15 STD RESET
XLXI_2/clkcnt<12> 4 18 FB1_16 STD RESET
XLXI_2/clkcnt<11> 4 18 FB1_17 STD RESET
XLXI_2/clkcnt<10> 4 18 FB1_18 STD RESET
XLXI_2/ddram_1_ddram<5>/XLXI_2/ddram_1_ddram<5>_RSTF 2 6 FB2_3 STD
XLXI_1/count<0> 2 2 FB2_4 STD RESET
$OpTx$FX_DC$41 2 3 FB2_5 STD
XLXN_1 3 5 FB2_6 STD RESET
XLXI_2/flag 3 5 FB2_7 STD RESET
XLXI_2/ddram_1_ddram<3>/XLXI_2/ddram_1_ddram<3>_RSTF 3 6 FB2_8 STD
XLXI_1/count<2> 3 4 FB2_9 STD RESET
XLXI_1/count<1> 3 3 FB2_10 STD RESET
XLXI_2/state_FFd2 4 6 FB2_11 STD RESET
XLXI_2/ddram_1_ddram<2>/XLXI_2/ddram_1_ddram<2>_SETF 4 6 FB2_12 STD
XLXI_2/ddram_1_ddram<1>/XLXI_2/ddram_1_ddram<1>_SETF 4 6 FB2_13 STD
$OpTx$$OpTx$INV$38_INV$147 4 6 FB2_14 STD
XLXI_2/ddram_1_ddram<0>/XLXI_2/ddram_1_ddram<0>_SETF 5 6 FB2_15 STD
XLXI_2/ddram_1_ddram<0>/XLXI_2/ddram_1_ddram<0>_RSTF 5 6 FB2_16 STD
XLXI_2/Mtrien_data<6> 6 10 FB2_17 STD RESET
XLXI_2/Mtrien_data<5> 6 10 FB2_18 STD RESET
XLXI_2/ddram_1_ddram<6> 1 3 FB3_13 STD RESET
XLXI_2/ddram_1_ddram<5> 2 6 FB3_14 STD RESET
XLXI_2/ddram_1_ddram<3> 2 6 FB3_15 STD RESET
XLXI_2/ddram_1_ddram<2> 2 2 FB3_16 STD RESET
XLXI_2/ddram_1_ddram<1> 2 4 FB3_17 STD RESET
XLXI_2/ddram_1_ddram<0> 2 2 FB3_18 STD RESET
$OpTx$$OpTx$FX_DC$39_INV$146 1 2 FB4_3 STD
XLXI_2/clk_int 2 3 FB4_4 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXI_2/address<5> 3 5 FB4_5 STD RESET
XLXI_2/address<4> 3 5 FB4_6 STD RESET
XLXI_2/state_FFd3 4 5 FB4_7 STD RESET
XLXI_2/address<3> 5 11 FB4_8 STD RESET
XLXI_2/address<2> 6 11 FB4_12 STD RESET
XLXI_2/Mtrien_data<1> 6 10 FB4_13 STD RESET
XLXI_2/address<1> 7 11 FB4_14 STD RESET
XLXI_2/address<0> 5 10 FB4_16 STD RESET
XLXI_2/clkdiv 2 18 FB5_18 STD RESET
XLXI_2/state_FFd1 7 9 FB8_1 STD RESET
XLXI_2/Mtrien_data<0> 6 10 FB8_2 STD RESET
XLXI_2/Mtrien_data<2> 6 10 FB8_3 STD RESET
XLXI_2/Mtrien_data<3> 6 10 FB8_5 STD RESET
XLXI_2/Mtrien_data<4> 6 10 FB8_6 STD RESET
data<5>_BUFR 9 11 FB8_17 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
rst FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 18/36
Number of signals used by logic mapping into function block: 18
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
XLXI_2/clkcnt<9> 3 0 0 2 FB1_3 17 I/O (b)
XLXI_2/clkcnt<8> 3 0 0 2 FB1_4 25 I/O (b)
XLXI_2/clkcnt<7> 3 0 0 2 FB1_5 19 I/O (b)
XLXI_2/clkcnt<5> 3 0 0 2 FB1_6 20 I/O (b)
XLXI_2/clkcnt<4> 3 0 0 2 FB1_7 (b) (b)
XLXI_2/clkcnt<3> 3 0 0 2 FB1_8 21 I/O (b)
XLXI_2/clkcnt<2> 3 0 0 2 FB1_9 22 I/O (b)
XLXI_2/clkcnt<1> 3 0 0 2 FB1_10 31 I/O (b)
XLXI_2/clkcnt<14> 3 0 0 2 FB1_11 24 I/O (b)
XLXI_2/clkcnt<13> 3 0 0 2 FB1_12 26 I/O (b)
XLXI_2/clkcnt<0> 3 0 0 2 FB1_13 (b) (b)
XLXI_2/clkcnt<6> 4 0 0 1 FB1_14 27 I/O (b)
XLXI_2/clkcnt<15> 4 0 0 1 FB1_15 28 I/O (b)
XLXI_2/clkcnt<12> 4 0 0 1 FB1_16 35 I/O (b)
XLXI_2/clkcnt<11> 4 0 0 1 FB1_17 30 GCK/I/O (b)
XLXI_2/clkcnt<10> 4 0 0 1 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: XLXI_2/clkcnt<0> 7: XLXI_2/clkcnt<15> 13: XLXI_2/clkcnt<6>
2: XLXI_2/clkcnt<10> 8: XLXI_2/clkcnt<1> 14: XLXI_2/clkcnt<7>
3: XLXI_2/clkcnt<11> 9: XLXI_2/clkcnt<2> 15: XLXI_2/clkcnt<8>
4: XLXI_2/clkcnt<12> 10: XLXI_2/clkcnt<3> 16: XLXI_2/clkcnt<9>
5: XLXI_2/clkcnt<13> 11: XLXI_2/clkcnt<4> 17: XLXN_1
6: XLXI_2/clkcnt<14> 12: XLXI_2/clkcnt<5> 18: rst
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
XLXI_2/clkcnt<9> X......XXXXXXXXXXX...................... 12
XLXI_2/clkcnt<8> X......XXXXXXXX.XX...................... 11
XLXI_2/clkcnt<7> X......XXXXXXX..XX...................... 10
XLXI_2/clkcnt<5> X......XXXXX....XX...................... 8
XLXI_2/clkcnt<4> X......XXXX.....XX...................... 7
XLXI_2/clkcnt<3> X......XXX......XX...................... 6
XLXI_2/clkcnt<2> X......XX.......XX...................... 5
XLXI_2/clkcnt<1> X......X........XX...................... 4
XLXI_2/clkcnt<14> XXXXXX.XXXXXXXXXXX...................... 17
XLXI_2/clkcnt<13> XXXXX..XXXXXXXXXXX...................... 16
XLXI_2/clkcnt<0> XXXXXXXXXXXXXXXXXX...................... 18
XLXI_2/clkcnt<6> XXXXXXXXXXXXXXXXXX...................... 18
XLXI_2/clkcnt<15> XXXXXXXXXXXXXXXXXX...................... 18
XLXI_2/clkcnt<12> XXXXXXXXXXXXXXXXXX...................... 18
XLXI_2/clkcnt<11> XXXXXXXXXXXXXXXXXX...................... 18
XLXI_2/clkcnt<10> XXXXXXXXXXXXXXXXXX...................... 18
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 18/36
Number of signals used by logic mapping into function block: 18
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\2 3 FB2_1 142 I/O (b)
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
XLXI_2/ddram_1_ddram<5>/XLXI_2/ddram_1_ddram<5>_RSTF
2 0 0 3 FB2_3 (b) (b)
XLXI_1/count<0> 2 0 0 3 FB2_4 4 I/O (b)
$OpTx$FX_DC$41 2 0 0 3 FB2_5 2 GTS/I/O (b)
XLXN_1 3 0 0 2 FB2_6 3 GTS/I/O (b)
XLXI_2/flag 3 0 0 2 FB2_7 (b) (b)
XLXI_2/ddram_1_ddram<3>/XLXI_2/ddram_1_ddram<3>_RSTF
3 0 0 2 FB2_8 5 GTS/I/O (b)
XLXI_1/count<2> 3 0 0 2 FB2_9 6 GTS/I/O (b)
XLXI_1/count<1> 3 0 0 2 FB2_10 7 I/O (b)
XLXI_2/state_FFd2 4 0 0 1 FB2_11 9 I/O (b)
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