📄 ps2.vf
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 7.1i
// \ \ Application : sch2verilog
// / / Filename : ps2.vf
// /___/ /\ Timestamp : 03/14/2006 15:33:32
// \ \ / \
// \___\/\___\
//
//Command: D:/Xilinx/bin/nt/sch2verilog.exe -intstyle ise -family spartan2 -w ps2.sch ps2.vf
//Design Name: ps2
//Device: spartan2
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module ps2(clk,
rst,
dataout,
ps2_clk,
ps2_data);
input clk;
input rst;
output [7:0] dataout;
inout ps2_clk;
inout ps2_data;
wire XLXN_4;
wire XLXN_5;
wire [7:0] XLXN_6;
wire XLXN_12;
ps2_keyboard_interface XLXI_2 (.clk(XLXN_12),
.reset(rst),
.rx_read(XLXN_4),
.tx_data(XLXN_6[7:0]),
.tx_write(XLXN_5),
.rx_ascii(dataout[7:0]),
.rx_data_ready(),
.rx_extended(),
.rx_released(),
.rx_scan_code(),
.rx_shift_key_on(),
.tx_error_no_keyboard_ack(),
.tx_write_ack_o(),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data));
div_256 XLXI_4 (.mclk(clk),
.reset(rst),
.clk(XLXN_12));
initial1 XLXI_5 (.rx_read(XLXN_4),
.tx_data(XLXN_6[7:0]),
.tx_write(XLXN_5));
endmodule
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