ps2.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

WARNING:Xst:1291 - FF/Latch <XLXI_2/rx_scan_code_0> is unconnected in block <ps2>.
WARNING:Xst:1291 - FF/Latch <XLXI_2/rx_scan_code_1> is unconnected in block <ps2>.
WARNING:Xst:1291 - FF/Latch <XLXI_2/rx_scan_code_2> is unconnected in block <ps2>.
WARNING:Xst:1291 - FF/Latch <XLXI_2/rx_scan_code_3> is unconnected in block <ps2>.
WARNING:Xst:1291 - FF/Latch <XLXI_2/rx_scan_code_4> is unconnected in block <ps2>.
WARNING:Xst:1291 - FF/Latch <XLXI_2/rx_scan_code_7> is unconnected in block <ps2>.
WARNING:Xst:1291 - FF/Latch <XLXI_2/rx_released> is unconnected in block <ps2>.
WARNING:Xst:1291 - FF/Latch <XLXI_2/rx_extended> is unconnected in block <ps2>.
WARNING:Xst:1291 - FF/Latch <XLXI_2/hold_extended> is unconnected in block <ps2>.

Optimizing unit <ps2> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ps2, actual ratio is 18.
FlipFlop XLXI_2/m1_state_0 has been replicated 1 time(s)
FlipFlop XLXI_2/m1_state_1 has been replicated 2 time(s)
FlipFlop XLXI_2/m1_state_2 has been replicated 1 time(s)
FlipFlop XLXI_2/m1_state_3 has been replicated 1 time(s)
FlipFlop XLXI_2/q_1 has been replicated 2 time(s)
FlipFlop XLXI_2/q_2 has been replicated 3 time(s)
FlipFlop XLXI_2/q_3 has been replicated 3 time(s)
FlipFlop XLXI_2/q_4 has been replicated 6 time(s)
FlipFlop XLXI_2/q_5 has been replicated 6 time(s)
FlipFlop XLXI_2/q_6 has been replicated 5 time(s)
FlipFlop XLXI_2/q_7 has been replicated 5 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ps2.ngr
Top Level Output File Name         : ps2
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# Registers                        : 21
#      1-bit register              : 14
#      11-bit register             : 1
#      7-bit register              : 1
#      8-bit register              : 5
# Multiplexers                     : 1
#      1-bit 4-to-1 multiplexer    : 1
# Tristates                        : 2
#      1-bit tristate buffer       : 2
# Adders/Subtractors               : 4
#      7-bit adder                 : 1
#      8-bit adder                 : 3
# Xors                             : 1
#      1-bit xor8                  : 1

Cell Usage :
# BELS                             : 302
#      GND                         : 1
#      INV                         : 5
#      LUT1                        : 23
#      LUT2                        : 14
#      LUT2_D                      : 2
#      LUT2_L                      : 5
#      LUT3                        : 25
#      LUT3_D                      : 2
#      LUT3_L                      : 13
#      LUT4                        : 81
#      LUT4_D                      : 10
#      LUT4_L                      : 61
#      MUXCY                       : 24
#      MUXF5                       : 11
#      VCC                         : 1
#      XORCY                       : 24
# FlipFlops/Latches                : 94
#      FD                          : 2
#      FDC                         : 7
#      FDE                         : 1
#      FDR                         : 2
#      FDRE                        : 73
#      FDRS                        : 7
#      FDS                         : 2
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 1
#      IOBUF                       : 2
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                     134  out of    768    17%  
 Number of Slice Flip Flops:            94  out of   1536     6%  
 Number of 4 input LUTs:               236  out of   1536    15%  
 Number of bonded IOBs:                 12  out of     96    12%  
 Number of GCLKs:                        2  out of      4    50%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_4/clk:Q                       | BUFG                   | 86    |
clk                                | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 11.470ns (Maximum Frequency: 87.184MHz)
   Minimum input arrival time before clock: 9.460ns
   Maximum output required time after clock: 12.643ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_4/clk:Q'
  Clock period: 11.470ns (frequency: 87.184MHz)
  Total number of paths / destination ports: 1644 / 188
-------------------------------------------------------------------------
Delay:               11.470ns (Levels of Logic = 5)
  Source:            XLXI_2/left_shift_key (FF)
  Destination:       XLXI_2/rx_ascii_6 (FF)
  Source Clock:      XLXI_4/clk:Q rising
  Destination Clock: XLXI_4/clk:Q rising

  Data Path: XLXI_2/left_shift_key to XLXI_2/rx_ascii_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             18   1.292   3.000  XLXI_2/left_shift_key (XLXI_2/left_shift_key)
     LUT2_D:I0->O         10   0.653   2.200  XLXI_2/rx_shift_key_on1 (XLXI_2/rx_shift_key_on)
     LUT4_L:I2->LO         1   0.653   0.100  XLXI_2/ascii<6>72 (CHOICE2436)
     LUT4:I2->O            1   0.653   1.150  XLXI_2/ascii<6>121 (CHOICE2447)
     LUT4_L:I1->LO         1   0.653   0.000  XLXI_2/ascii<6>3661_G (N2261)
     MUXF5:I1->O           1   0.363   0.000  XLXI_2/ascii<6>3661 (XLXI_2/ascii<6>)
     FDRE:D                    0.753          XLXI_2/rx_ascii_6
    ----------------------------------------
    Total                     11.470ns (5.020ns logic, 6.450ns route)
                                       (43.8% logic, 56.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.382ns (frequency: 185.805MHz)
  Total number of paths / destination ports: 35 / 8
-------------------------------------------------------------------------
Delay:               5.382ns (Levels of Logic = 8)
  Source:            XLXI_4/count_0 (FF)
  Destination:       XLXI_4/clk (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_4/count_0 to XLXI_4/clk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   1.292   1.150  XLXI_4/count_0 (XLXI_4/count_0)
     INV:I->O              2   0.653   0.000  ps2_XLXI_4/_old_count_8<0>lut_INV_0 (XLXI_4/_old_count_8<0>)
     MUXCY:S->O            1   0.784   0.000  ps2_XLXI_4/_old_count_8<0>cy (ps2_XLXI_4/_old_count_8<0>_cyo)
     MUXCY:CI->O           1   0.050   0.000  ps2_XLXI_4/_old_count_8<1>cy (ps2_XLXI_4/_old_count_8<1>_cyo)
     MUXCY:CI->O           1   0.050   0.000  ps2_XLXI_4/_old_count_8<2>cy (ps2_XLXI_4/_old_count_8<2>_cyo)
     MUXCY:CI->O           1   0.050   0.000  ps2_XLXI_4/_old_count_8<3>cy (ps2_XLXI_4/_old_count_8<3>_cyo)
     MUXCY:CI->O           1   0.050   0.000  ps2_XLXI_4/_old_count_8<4>cy (ps2_XLXI_4/_old_count_8<4>_cyo)
     MUXCY:CI->O           0   0.050   0.000  ps2_XLXI_4/_old_count_8<5>cy (ps2_XLXI_4/_old_count_8<5>_cyo)
     XORCY:CI->O           2   0.500   0.000  ps2_XLXI_4/_old_count_8<6>_xor (XLXI_4/_old_count_8<6>)
     FDC:D                     0.753          XLXI_4/count_6
    ----------------------------------------
    Total                      5.382ns (4.232ns logic, 1.150ns route)
                                       (78.6% logic, 21.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_4/clk:Q'
  Total number of paths / destination ports: 66 / 66
-------------------------------------------------------------------------
Offset:              9.460ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       XLXI_2/m1_state_1 (FF)
  Destination Clock: XLXI_4/clk:Q rising

  Data Path: rst to XLXI_2/m1_state_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.924   1.600  rst_IBUF (rst_IBUF)
     INV:I->O             66   0.653   5.500  XLXI_2/m1_state_3_N01_INV_0 (XLXI_2/m1_state_3_N0)
     FDRS:R                    0.783          XLXI_2/m1_state_3
    ----------------------------------------
    Total                      9.460ns (2.360ns logic, 7.100ns route)
                                       (24.9% logic, 75.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              3.410ns (Levels of Logic = 1)
  Source:            rst (PAD)
  Destination:       XLXI_4/clk (FF)
  Destination Clock: clk rising

  Data Path: rst to XLXI_4/clk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.924   1.600  rst_IBUF (rst_IBUF)
     FDE:CE                    0.886          XLXI_4/clk
    ----------------------------------------
    Total                      3.410ns (1.810ns logic, 1.600ns route)
                                       (53.1% logic, 46.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_4/clk:Q'
  Total number of paths / destination ports: 20 / 9
-------------------------------------------------------------------------
Offset:              12.643ns (Levels of Logic = 3)
  Source:            XLXI_2/m1_state_1 (FF)
  Destination:       ps2_data (PAD)
  Source Clock:      XLXI_4/clk:Q rising

  Data Path: XLXI_2/m1_state_1 to ps2_data
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q            25   1.292   3.450  XLXI_2/m1_state_1 (XLXI_2/m1_state_1)
     LUT4:I3->O            1   0.653   0.000  XLXI_2/ps2_data_hi_z111_F (N2138)
     MUXF5:I0->O           1   0.375   1.150  XLXI_2/ps2_data_hi_z111 (XLXI_2/ps2_data_hi_z)
     IOBUF:T->IO               5.723          ps2_data_IOBUF (ps2_data)
    ----------------------------------------
    Total                     12.643ns (8.043ns logic, 4.600ns route)
                                       (63.6% logic, 36.4% route)

=========================================================================
CPU : 18.21 / 18.64 s | Elapsed : 18.00 / 18.00 s
 
--> 

Total memory usage is 77220 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   28 (   0 filtered)
Number of infos    :    0 (   0 filtered)