ps2.mrp

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1i Map H.38
Xilinx Mapping Report File for Design 'ps2'

Design Information
------------------
Command Line   : D:/Xilinx/bin/nt/map.exe -ise
e:\temp\spartan2\veriloge\interface\ps2\ps2.ise -intstyle ise -p xc2s50-tq144-5
-cm area -pr b -k 4 -c 100 -tx off -o ps2_map.ncd ps2.ngd ps2.pcf 
Target Device  : xc2s50
Target Package : tq144
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.26.6.3 $
Mapped Date    : Tue Mar 14 15:34:00 2006

Design Summary
--------------
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        85 out of  1,536    5%
  Number of 4 input LUTs:           216 out of  1,536   14%
Logic Distribution:
    Number of occupied Slices:                         150 out of    768   19%
    Number of Slices containing only related logic:    150 out of    150  100%
    Number of Slices containing unrelated logic:         0 out of    150    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          240 out of  1,536   15%
      Number used as logic:                       216
      Number used as a route-thru:                 24
   Number of bonded IOBs:            11 out of     92   11%
      IOB Flip Flops:                               9
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  2,231
Additional JTAG gate count for IOBs:  576
Peak Memory Usage:  86 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| dataout<0>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| dataout<1>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| dataout<2>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| dataout<3>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| dataout<4>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| dataout<5>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| dataout<6>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| dataout<7>                         | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| ps2_clk                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| ps2_data                           | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     |          | IFD   |
| rst                                | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
--------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 12
Number of Equivalent Gates for Design = 2,231
Number of RPM Macros = 0
Number of Hard Macros = 0
PCI IOBs = 0
PCI LOGICs = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
DLLs = 0
GCLKIOBs = 1
GCLKs = 2
Block RAMs = 0
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 71
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 3
IOB Flip Flops = 9
Unbonded IOBs = 0
Bonded IOBs = 11
XORs = 24
CARRY_INITs = 14
CARRY_SKIPs = 0
CARRY_MUXes = 24
Shift Registers = 0
Static Shift Registers = 0
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MULT_ANDs = 0
MUXF5s + MUXF6s = 11
4 input LUTs used as Route-Thrus = 24
4 input LUTs = 216
Slice Latches not driven by LUTs = 0
Slice Latches = 0
Slice Flip Flops not driven by LUTs = 68
Slice Flip Flops = 85
Slices = 150
F6 Muxes = 0
F5 Muxes = 11
Number of LUT signals with 4 loads = 1
Number of LUT signals with 3 loads = 4
Number of LUT signals with 2 loads = 20
Number of LUT signals with 1 load = 181
NGM Average fanout of LUT = 1.67
NGM Maximum fanout of LUT = 45
NGM Average fanin for LUT = 3.5880
Number of LUT symbols = 216