📄 ps2.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: ps2 Date: 2-25-2006, 6:12PM
Device Used: XC95144XL-5-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
73 /144 ( 51%) 481 /720 ( 67%) 163/432 ( 38%) 59 /144 ( 41%) 12 /117 ( 10%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 13/18 32/54 89/90 0/15
FB2 10/18 23/54 87/90 0/15
FB3 10/18 23/54 55/90 8/15
FB4 7/18 21/54 88/90 0/15
FB5 16/18 32/54 72/90 0/14
FB6 2/18 3/54 4/90 0/13
FB7 15/18 29/54 86/90 2/15
FB8 0/18 0/54 0/90 0/15
----- ----- ----- -----
73/144 163/432 481/720 10/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 12 109
Output : 8 8 | GCK/IO : 0 3
Bidirectional : 2 2 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 12 12
** Power Data **
There are 73 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
because too many function block product terms are required. Buffering output
signal led<6> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
because too many function block product terms are required. Buffering output
signal led<0> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
because too many function block product terms are required. Buffering output
signal led<5> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
because too many function block product terms are required. Buffering output
signal led<4> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
because too many function block product terms are required. Buffering output
signal led<2> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
because too many function block product terms are required. Buffering output
signal led<1> to allow all signals assigned to this function block to be
placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB3,
because too many function block product terms are required. Buffering output
signal led<3> to allow all signals assigned to this function block to be
placed.
************************* Summary of Mapped Logic ************************
** 10 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
led<5> 1 1 FB3_5 33 I/O O STD FAST
led<4> 1 1 FB3_9 40 I/O O STD FAST
led<7> 0 0 FB3_10 48 I/O O STD FAST
led<3> 1 1 FB3_11 43 I/O O STD FAST
led<2> 1 1 FB3_12 45 I/O O STD FAST
led<1> 1 1 FB3_14 49 I/O O STD FAST
led<6> 1 1 FB3_15 50 I/O O STD FAST
led<0> 1 1 FB3_17 51 I/O O STD FAST
ps2_clk 1 4 FB7_15 87 I/O I/O STD FAST
ps2_data 1 1 FB7_17 88 I/O I/O STD FAST
** 63 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXI_2/timer_5usec_count<4> 5 9 FB1_1 STD RESET
XLXI_2/timer_60usec_count<5> 6 11 FB1_3 STD RESET
XLXI_2/timer_60usec_count<4> 6 10 FB1_4 STD RESET
XLXI_2/timer_60usec_count<3> 6 9 FB1_5 STD RESET
XLXI_2/timer_60usec_count<2> 6 8 FB1_6 STD RESET
XLXI_2/bit_count<3> 6 23 FB1_7 STD RESET
XLXI_2/bit_count<2> 6 23 FB1_9 STD RESET
XLXI_2/bit_count<1> 6 23 FB1_10 STD RESET
XLXI_2/bit_count<0> 6 23 FB1_11 STD RESET
XLXI_2/m1_state<1> 12 20 FB1_12 STD RESET
XLXI_2/m1_state<0> 14 32 FB1_15 STD RESET
XLXI_2/timer_5usec_count<6> 5 11 FB1_17 STD RESET
XLXI_2/timer_5usec_count<5> 5 10 FB1_18 STD RESET
led<0>_BUFR 26 17 FB2_2 STD RESET
XLXI_2/right_shift_key 4 16 FB2_5 STD RESET
XLXI_2/q<4> 4 7 FB2_6 STD RESET
XLXI_2/q<3> 4 7 FB2_7 STD RESET
XLXI_2/q<2> 4 7 FB2_8 STD RESET
XLXI_2/q<1> 4 7 FB2_9 STD RESET
XLXI_2/left_shift_key 4 16 FB2_10 STD RESET
$OpTx$INV$742 5 12 FB2_11 STD
XLXI_2/hold_released 7 15 FB2_12 STD RESET
led<4>_BUFR 25 16 FB2_15 STD RESET
led<6>_BUFR 26 17 FB3_1 STD RESET
led<3>_BUFR 22 17 FB3_7 STD RESET
led<1>_BUFR 23 14 FB4_3 STD RESET
XLXI_2/q<0> 4 7 FB4_5 STD RESET
XLXI_2/q<5> 4 7 FB4_6 STD RESET
XLXI_2/q<6> 4 7 FB4_7 STD RESET
XLXI_2/q<7> 4 7 FB4_8 STD RESET
led<5>_BUFR 25 15 FB4_11 STD RESET
led<2>_BUFR 24 14 FB4_16 STD RESET
XLXI_2/rx_ascii_4__n000093/XLXI_2/rx_ascii_4__n000093_D2 22 9 FB5_1 STD
$OpTx$$OpTx$FX_DC$743_INV$1450 1 2 FB5_3 STD
XLXI_4/count<0> 2 2 FB5_4 STD RESET
XLXI_4/count<6> 3 8 FB5_5 STD RESET
XLXI_4/count<5> 3 7 FB5_6 STD RESET
XLXI_4/count<4> 3 6 FB5_7 STD RESET
XLXI_4/count<3> 3 5 FB5_8 STD RESET
XLXI_4/count<2> 3 4 FB5_9 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
XLXI_4/count<1> 3 3 FB5_10 STD RESET
led_7_OBUF/led_7_OBUF_TRST 4 5 FB5_11 STD
XLXN_12 4 9 FB5_12 STD RESET
XLXI_2/timer_5usec_count<2> 4 7 FB5_13 STD RESET
XLXI_2/q<9> 4 7 FB5_14 STD RESET
XLXI_2/q<8> 4 7 FB5_15 STD RESET
XLXI_2/q<10> 4 7 FB5_16 STD RESET
XLXI_2/timer_5usec_count<3> 5 8 FB5_17 STD RESET
XLXI_2/ps2_data_s 2 2 FB6_17 STD RESET
XLXI_2/ps2_clk_s 2 2 FB6_18 STD RESET
XLXI_2/timer_60usec_count<0> 5 17 FB7_2 STD RESET
XLXI_2/timer_5usec_count<7> 5 12 FB7_3 STD RESET
XLXI_2/timer_60usec_count<9> 6 15 FB7_4 STD RESET
XLXI_2/timer_60usec_count<8> 6 14 FB7_5 STD RESET
XLXI_2/timer_60usec_count<7> 6 13 FB7_6 STD RESET
XLXI_2/timer_60usec_count<6> 6 12 FB7_7 STD RESET
XLXI_2/timer_60usec_count<11> 6 17 FB7_9 STD RESET
XLXI_2/timer_60usec_count<10> 6 16 FB7_10 STD RESET
XLXI_2/timer_5usec_count<1> 6 12 FB7_11 STD RESET
XLXI_2/timer_60usec_count<1> 7 17 FB7_12 STD RESET
XLXI_2/m1_state<2> 10 16 FB7_14 STD RESET
XLXI_2/m1_state<3> 12 28 FB7_16 STD RESET
XLXI_2/timer_5usec_count<0> 3 12 FB7_18 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
rst FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 32/22
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
XLXI_2/timer_5usec_count<4>
5 0 0 0 FB1_1 23 I/O (b)
(unused) 0 0 \/5 0 FB1_2 16 I/O (b)
XLXI_2/timer_60usec_count<5>
6 5<- \/4 0 FB1_3 17 I/O (b)
XLXI_2/timer_60usec_count<4>
6 4<- \/3 0 FB1_4 25 I/O (b)
XLXI_2/timer_60usec_count<3>
6 3<- \/2 0 FB1_5 19 I/O (b)
XLXI_2/timer_60usec_count<2>
6 2<- \/1 0 FB1_6 20 I/O (b)
XLXI_2/bit_count<3> 6 1<- 0 0 FB1_7 (b) (b)
(unused) 0 0 \/5 0 FB1_8 21 I/O (b)
XLXI_2/bit_count<2> 6 5<- \/4 0 FB1_9 22 I/O (b)
XLXI_2/bit_count<1> 6 4<- \/3 0 FB1_10 31 I/O (b)
XLXI_2/bit_count<0> 6 3<- \/2 0 FB1_11 24 I/O (b)
XLXI_2/m1_state<1> 12 7<- 0 0 FB1_12 26 I/O (b)
(unused) 0 0 /\5 0 FB1_13 (b) (b)
(unused) 0 0 \/5 0 FB1_14 27 I/O (b)
XLXI_2/m1_state<0> 14 9<- 0 0 FB1_15 28 I/O (b)
(unused) 0 0 /\4 1 FB1_16 35 I/O (b)
XLXI_2/timer_5usec_count<6>
5 0 0 0 FB1_17 30 GCK/I/O (b)
XLXI_2/timer_5usec_count<5>
5 0 0 0 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: XLXI_2/bit_count<0> 12: XLXI_2/timer_5usec_count<1> 23: XLXI_2/timer_60usec_count<2>
2: XLXI_2/bit_count<1> 13: XLXI_2/timer_5usec_count<2> 24: XLXI_2/timer_60usec_count<3>
3: XLXI_2/bit_count<2> 14: XLXI_2/timer_5usec_count<3> 25: XLXI_2/timer_60usec_count<4>
4: XLXI_2/bit_count<3> 15: XLXI_2/timer_5usec_count<4> 26: XLXI_2/timer_60usec_count<5>
5: XLXI_2/m1_state<0> 16: XLXI_2/timer_5usec_count<5> 27: XLXI_2/timer_60usec_count<6>
6: XLXI_2/m1_state<1> 17: XLXI_2/timer_5usec_count<6> 28: XLXI_2/timer_60usec_count<7>
7: XLXI_2/m1_state<2> 18: XLXI_2/timer_5usec_count<7> 29: XLXI_2/timer_60usec_count<8>
8: XLXI_2/m1_state<3> 19: XLXI_2/timer_60usec_count<0> 30: XLXI_2/timer_60usec_count<9>
9: XLXI_2/ps2_clk_s 20: XLXI_2/timer_60usec_count<10> 31: XLXN_12
10: XLXI_2/ps2_data_s 21: XLXI_2/timer_60usec_count<11> 32: rst
11: XLXI_2/timer_5usec_count<0> 22: XLXI_2/timer_60usec_count<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
XLXI_2/timer_5usec_count<4>
....XXX...XXXXX...............X......... 9
XLXI_2/timer_60usec_count<5>
....XXXX..........X..XXXXX....X......... 11
XLXI_2/timer_60usec_count<4>
....XXXX..........X..XXXX.....X......... 10
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