buzzer.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: buzzer.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "buzzer.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "buzzer"
Output Format                      : NGC
Target Device                      : xc2s50-6-TQ144

---- Source Options
Top Module Name                    : buzzer
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : buzzer.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "buzzer.v"
Module <buzzer> compiled
No errors in compilation
Analysis of file <"buzzer.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <buzzer>.
	duo = 3822
	lai = 3405
	mi = 3034
	fa = 2865
	suo = 2551
	la = 2273
	xi = 2024
	duo1 = 1911
Module <buzzer> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <buzzer>.
    Related source file is "buzzer.v".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state> of Case statement line 49 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'init' attribute on signal <state> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 16                                             |
    | Inputs             | 1                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0000 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <out>.
    Found 22-bit adder for signal <$n0012> created at line 49.
    Found 13-bit adder for signal <$n0014> created at line 49.
    Found 4-bit up counter for signal <clk_div1>.
    Found 13-bit register for signal <clk_div2>.
    Found 22-bit register for signal <cnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  36 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <buzzer> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 011
 011   | 010
 100   | 110
 101   | 111
 110   | 101
 111   | 100
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 2
 13-bit adder                      : 1
 22-bit adder                      : 1
# Counters                         : 1
 4-bit up counter                  : 1
# Registers                        : 6
 1-bit register                    : 4
 13-bit register                   : 1
 22-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <buzzer> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block buzzer, actual ratio is 7.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : buzzer.ngr
Top Level Output File Name         : buzzer
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 3

Macro Statistics :
# Registers                        : 4
#      1-bit register              : 1
#      13-bit register             : 1
#      22-bit register             : 1
#      4-bit register              : 1
# Adders/Subtractors               : 3
#      13-bit adder                : 1
#      22-bit adder                : 1
#      4-bit adder                 : 1

Cell Usage :
# BELS                             : 182
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 33
#      LUT2                        : 5
#      LUT2_D                      : 1
#      LUT3                        : 2
#      LUT3_D                      : 1
#      LUT4                        : 39
#      LUT4_D                      : 6
#      LUT4_L                      : 23
#      MUXCY                       : 33
#      VCC                         : 1
#      XORCY                       : 33
# FlipFlops/Latches                : 43
#      FDR                         : 4
#      FDRE                        : 39
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 2
#      IBUF                        : 1
#      OBUF                        : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      61  out of    768     7%  
 Number of Slice Flip Flops:            43  out of   1536     2%  
 Number of 4 input LUTs:               110  out of   1536     7%  
 Number of bonded IOBs:                  3  out of     96     3%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 43    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.849ns (Maximum Frequency: 84.395MHz)
   Minimum input arrival time before clock: 7.000ns
   Maximum output required time after clock: 6.959ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 11.849ns (frequency: 84.395MHz)
  Total number of paths / destination ports: 2390 / 86
-------------------------------------------------------------------------
Delay:               11.849ns (Levels of Logic = 6)
  Source:            clk_div2_0 (FF)
  Destination:       out (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: clk_div2_0 to out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            10   1.085   1.980  clk_div2_0 (clk_div2_0)
     LUT4:I0->O            1   0.549   1.035  Ker7_SW2 (N269)
     LUT4:I3->O            2   0.549   1.206  _n0025 (_n0025)
     LUT4_L:I2->LO         1   0.549   0.100  Ker049 (CHOICE42)
     LUT4:I1->O           14   0.549   2.340  Ker064 (CHOICE44)
     LUT4_L:I3->LO         1   0.549   0.100  Ker0123 (N01)
     LUT4_L:I3->LO         1   0.549   0.000  _n0013121 (_n0013)
     FDRE:D                    0.709          out
    ----------------------------------------
    Total                     11.849ns (5.088ns logic, 6.761ns route)
                                       (42.9% logic, 57.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 43 / 43
-------------------------------------------------------------------------
Offset:              7.000ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       clk_div2_12 (FF)
  Destination Clock: clk rising

  Data Path: rst to clk_div2_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.776   1.206  rst_IBUF (rst_IBUF)
     INV:I->O             39   0.549   3.735  state_FFd3_N01_INV_0 (state_FFd3_N0)
     FDRE:R                    0.734          state_FFd3
    ----------------------------------------
    Total                      7.000ns (2.059ns logic, 4.941ns route)
                                       (29.4% logic, 70.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.959ns (Levels of Logic = 1)
  Source:            out (FF)
  Destination:       out (PAD)
  Source Clock:      clk rising

  Data Path: out to out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             2   1.085   1.206  out (out_OBUF)
     OBUF:I->O                 4.668          out_OBUF (out)
    ----------------------------------------
    Total                      6.959ns (5.753ns logic, 1.206ns route)
                                       (82.7% logic, 17.3% route)

=========================================================================
CPU : 11.99 / 12.71 s | Elapsed : 12.00 / 12.00 s
 
--> 

Total memory usage is 75780 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)