📄 buzzer.rpt
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cnt<5> XXXXX.............XXXXXX.X.............. 12
cnt<4> XXXXX.............XXXXX..X.............. 11
cnt<3> XXXXX.............XXXX...X.............. 10
cnt<2> XXXXX.............XXX....X.............. 9
cnt<1> XXXXX.............XX.....X.............. 8
cnt<0> XXXXX.............X......X.............. 7
clk_div2<12> XXXXXXXXXXXXXXXXXX.......X.............. 19
clk_div1<2> XXXX.....................X.............. 5
clk_div1<3> XXXXX....................X.............. 6
clk_div1<1> XXXXX....................X.............. 6
clk_div2<4> XXXXXXXXXXXXXXXXXX.......XXXX........... 22
clk_div2<10> XXXXXXXXXXXXXXXXXX.......XXXX........... 22
clk_div2<9> XXXXXXXXXXXXXXXXXX.......XXXX........... 22
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
(unused) 0 0 0 5 FB3_5 33 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
(unused) 0 0 0 5 FB3_9 40 I/O
(unused) 0 0 0 5 FB3_10 48 I/O
(unused) 0 0 0 5 FB3_11 43 I/O
(unused) 0 0 0 5 FB3_12 45 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 49 I/O
(unused) 0 0 0 5 FB3_15 50 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 51 I/O
(unused) 0 0 0 5 FB3_18 (b)
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB4_1 118 I/O
(unused) 0 0 0 5 FB4_2 126 I/O
(unused) 0 0 0 5 FB4_3 133 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 128 I/O I
(unused) 0 0 0 5 FB4_6 129 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 130 I/O
(unused) 0 0 0 5 FB4_9 131 I/O
(unused) 0 0 0 5 FB4_10 135 I/O
(unused) 0 0 0 5 FB4_11 132 I/O
(unused) 0 0 0 5 FB4_12 134 I/O
(unused) 0 0 0 5 FB4_13 137 I/O
(unused) 0 0 0 5 FB4_14 136 I/O
(unused) 0 0 0 5 FB4_15 138 I/O
(unused) 0 0 0 5 FB4_16 139 I/O
(unused) 0 0 0 5 FB4_17 140 I/O
(unused) 0 0 0 5 FB4_18 (b)
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 52 I/O
(unused) 0 0 0 5 FB5_3 59 I/O
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 53 I/O
(unused) 0 0 0 5 FB5_6 54 I/O
(unused) 0 0 0 5 FB5_7 66 I/O
(unused) 0 0 0 5 FB5_8 56 I/O
(unused) 0 0 0 5 FB5_9 57 I/O
(unused) 0 0 0 5 FB5_10 68 I/O
(unused) 0 0 0 5 FB5_11 58 I/O
(unused) 0 0 0 5 FB5_12 60 I/O
(unused) 0 0 0 5 FB5_13 70 I/O
(unused) 0 0 0 5 FB5_14 61 I/O
(unused) 0 0 0 5 FB5_15 64 I/O
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 69 I/O
(unused) 0 0 0 5 FB5_18 (b)
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 106 I/O
(unused) 0 0 0 5 FB6_3 (b)
(unused) 0 0 0 5 FB6_4 111 I/O
(unused) 0 0 0 5 FB6_5 110 I/O
(unused) 0 0 0 5 FB6_6 112 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 113 I/O
(unused) 0 0 0 5 FB6_9 116 I/O
(unused) 0 0 0 5 FB6_10 115 I/O
(unused) 0 0 0 5 FB6_11 119 I/O
(unused) 0 0 0 5 FB6_12 120 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 121 I/O
(unused) 0 0 0 5 FB6_15 124 I/O
(unused) 0 0 0 5 FB6_16 117 I/O
(unused) 0 0 0 5 FB6_17 125 I/O
(unused) 0 0 0 5 FB6_18 (b)
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 23/31
Number of signals used by logic mapping into function block: 23
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 /\5 0 FB7_1 (b) (b)
clk_div2<2> 5 1<- /\1 0 FB7_2 71 I/O I
out 10 6<- /\1 0 FB7_3 75 I/O O
(unused) 0 0 /\5 0 FB7_4 (b) (b)
clk_div2<8> 9 5<- /\1 0 FB7_5 74 I/O (b)
(unused) 0 0 /\5 0 FB7_6 76 I/O (b)
(unused) 0 0 \/5 0 FB7_7 77 I/O (b)
clk_div2<5> 9 5<- \/1 0 FB7_8 78 I/O (b)
(unused) 0 0 \/5 0 FB7_9 80 I/O (b)
clk_div2<11> 9 6<- \/2 0 FB7_10 79 I/O (b)
(unused) 0 0 \/5 0 FB7_11 82 I/O (b)
clk_div2<0> 9 7<- \/3 0 FB7_12 85 I/O (b)
(unused) 0 0 \/5 0 FB7_13 81 I/O (b)
clk_div2<6> 10 8<- \/3 0 FB7_14 86 I/O (b)
clk_div2<1> 13 8<- 0 0 FB7_15 87 I/O (b)
(unused) 0 0 /\5 0 FB7_16 83 I/O (b)
(unused) 0 0 \/5 0 FB7_17 88 I/O (b)
clk_div2<3> 16 11<- 0 0 FB7_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 9: clk_div2<12> 17: clk_div2<8>
2: clk_div1<0> 10: clk_div2<1> 18: clk_div2<9>
3: clk_div1<1> 11: clk_div2<2> 19: out
4: clk_div1<2> 12: clk_div2<3> 20: rst
5: clk_div1<3> 13: clk_div2<4> 21: state_FFd1
6: clk_div2<0> 14: clk_div2<5> 22: state_FFd2
7: clk_div2<10> 15: clk_div2<6> 23: state_FFd3
8: clk_div2<11> 16: clk_div2<7>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
clk_div2<2> XXXXXXXXXXXXXXXXXX.XXXX................. 22
out XXXXXXXXXXXXXXXXXXXXXXX................. 23
clk_div2<8> XXXXXXXXXXXXXXXXXX.XXXX................. 22
clk_div2<5> XXXXXXXXXXXXXXXXXX.XXXX................. 22
clk_div2<11> XXXXXXXXXXXXXXXXXX.XXXX................. 22
clk_div2<0> XXXXXXXXXXXXXXXXXX.XXXX................. 22
clk_div2<6> XXXXXXXXXXXXXXXXXX.XXXX................. 22
clk_div2<1> XXXXXXXXXXXXXXXXXX.XXXX................. 22
clk_div2<3> XXXXXXXXXXXXXXXXXX.XXXX................. 22
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB8_1 (b)
(unused) 0 0 0 5 FB8_2 91 I/O
(unused) 0 0 0 5 FB8_3 95 I/O
(unused) 0 0 0 5 FB8_4 97 I/O
(unused) 0 0 0 5 FB8_5 92 I/O
(unused) 0 0 0 5 FB8_6 93 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 94 I/O
(unused) 0 0 0 5 FB8_9 96 I/O
(unused) 0 0 0 5 FB8_10 101 I/O
(unused) 0 0 0 5 FB8_11 98 I/O
(unused) 0 0 0 5 FB8_12 100 I/O
(unused) 0 0 0 5 FB8_13 103 I/O
(unused) 0 0 0 5 FB8_14 102 I/O
(unused) 0 0 0 5 FB8_15 104 I/O
(unused) 0 0 0 5 FB8_16 107 I/O
(unused) 0 0 0 5 FB8_17 105 I/O
(unused) 0 0 0 5 FB8_18 (b)
******************************* Equations ********************************
********** Mapped Logic **********
FDCPE FDCPE_clk_div10 (clk_div1[0],clk_div1_D[0],clk,1'b0,1'b0);
assign clk_div1_D[0] = (rst && !clk_div1[0]);
FDCPE FDCPE_clk_div11 (clk_div1[1],clk_div1_D[1],clk,1'b0,1'b0);
assign clk_div1_D[1] = ((clk_div1[3].EXP)
|| (rst && !clk_div1[0] && clk_div1[1])
|| (rst && clk_div1[0] && !clk_div1[1] && !clk_div1[3]));
FTCPE FTCPE_clk_div12 (clk_div1[2],clk_div1_T[2],clk,1'b0,1'b0);
assign clk_div1_T[2] = ((!rst && clk_div1[2])
|| (rst && clk_div1[0] && clk_div1[1]));
FTCPE FTCPE_clk_div13 (clk_div1[3],clk_div1_T[3],clk,1'b0,1'b0);
assign clk_div1_T[3] = ((!rst && clk_div1[3])
|| (rst && clk_div1[0] && clk_div1[1] && clk_div1[2])
|| (clk_div1[0] && !clk_div1[1] && !clk_div1[2] &&
clk_div1[3]));
FTCPE FTCPE_clk_div20 (clk_div2[0],clk_div2_T[0],clk,1'b0,1'b0);
assign clk_div2_T[0] = ((EXP17_.EXP)
|| (!clk_div2[0] && clk_div2[10] && clk_div2[11] &&
clk_div2[1] && clk_div2[2] && clk_div2[3] && !clk_div2[4] &&
clk_div2[5] && clk_div2[6] && clk_div2[7] && !clk_div2[8] &&
clk_div2[9] && !clk_div2[12] && !state_FFd1 && !state_FFd2 &&
!state_FFd3));
FDCPE FDCPE_clk_div21 (clk_div2[1],clk_div2_D[1],clk,1'b0,1'b0);
assign clk_div2_D[1] = ((clk_div2[6].EXP)
|| (EXP19_.EXP)
|| (!clk_div2[10] && clk_div2[11] && !clk_div2[1] &&
!clk_div2[2] && !clk_div2[3] && clk_div2[4] && clk_div2[5] &&
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