📄 buzzer.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: buzzer Date: 2-21-2006, 3:18PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
43 /144 ( 30%) 211 /720 ( 29%) 83 /432 ( 19%) 43 /144 ( 30%) 3 /117 ( 3%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 31/54 54/90 0/15
FB2 16/18 29/54 67/90 0/15
FB3 0/18 0/54 0/90 0/15
FB4 0/18 0/54 0/90 0/15
FB5 0/18 0/54 0/90 0/14
FB6 0/18 0/54 0/90 0/13
FB7 9/18 23/54 90/90* 1/15
FB8 0/18 0/54 0/90 0/15
----- ----- ----- -----
43/144 83/432 211/720 1/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 3 109
Output : 1 1 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 3 3
** Power Data **
There are 43 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 1 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
out 10 23 FB7_3 75 I/O O STD FAST RESET
** 42 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
state_FFd3 3 29 FB1_1 STD RESET
state_FFd2 3 30 FB1_2 STD RESET
state_FFd1 3 31 FB1_3 STD RESET
cnt<9> 3 16 FB1_4 STD RESET
cnt<8> 3 15 FB1_5 STD RESET
cnt<7> 3 14 FB1_6 STD RESET
cnt<21> 3 28 FB1_7 STD RESET
cnt<20> 3 27 FB1_8 STD RESET
cnt<19> 3 26 FB1_9 STD RESET
cnt<18> 3 25 FB1_10 STD RESET
cnt<17> 3 24 FB1_11 STD RESET
cnt<16> 3 23 FB1_12 STD RESET
cnt<15> 3 22 FB1_13 STD RESET
cnt<14> 3 21 FB1_14 STD RESET
cnt<13> 3 20 FB1_15 STD RESET
cnt<12> 3 19 FB1_16 STD RESET
cnt<11> 3 18 FB1_17 STD RESET
cnt<10> 3 17 FB1_18 STD RESET
clk_div2<7> 8 22 FB2_1 STD RESET
clk_div1<0> 2 3 FB2_3 STD RESET
cnt<6> 3 13 FB2_4 STD RESET
cnt<5> 3 12 FB2_5 STD RESET
cnt<4> 3 11 FB2_6 STD RESET
cnt<3> 3 10 FB2_7 STD RESET
cnt<2> 3 9 FB2_8 STD RESET
cnt<1> 3 8 FB2_9 STD RESET
cnt<0> 3 7 FB2_10 STD RESET
clk_div2<12> 3 19 FB2_11 STD RESET
clk_div1<2> 3 5 FB2_12 STD RESET
clk_div1<3> 4 6 FB2_13 STD RESET
clk_div1<1> 4 6 FB2_14 STD RESET
clk_div2<4> 7 22 FB2_15 STD RESET
clk_div2<10> 7 22 FB2_17 STD RESET
clk_div2<9> 8 22 FB2_18 STD RESET
clk_div2<2> 5 22 FB7_2 STD RESET
clk_div2<8> 9 22 FB7_5 STD RESET
clk_div2<5> 9 22 FB7_8 STD RESET
clk_div2<11> 9 22 FB7_10 STD RESET
clk_div2<0> 9 22 FB7_12 STD RESET
clk_div2<6> 10 22 FB7_14 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
clk_div2<1> 13 22 FB7_15 STD RESET
clk_div2<3> 16 22 FB7_18 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
rst FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 31/23
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
state_FFd3 3 0 0 2 FB1_1 23 I/O (b)
state_FFd2 3 0 0 2 FB1_2 16 I/O (b)
state_FFd1 3 0 0 2 FB1_3 17 I/O (b)
cnt<9> 3 0 0 2 FB1_4 25 I/O (b)
cnt<8> 3 0 0 2 FB1_5 19 I/O (b)
cnt<7> 3 0 0 2 FB1_6 20 I/O (b)
cnt<21> 3 0 0 2 FB1_7 (b) (b)
cnt<20> 3 0 0 2 FB1_8 21 I/O (b)
cnt<19> 3 0 0 2 FB1_9 22 I/O (b)
cnt<18> 3 0 0 2 FB1_10 31 I/O (b)
cnt<17> 3 0 0 2 FB1_11 24 I/O (b)
cnt<16> 3 0 0 2 FB1_12 26 I/O (b)
cnt<15> 3 0 0 2 FB1_13 (b) (b)
cnt<14> 3 0 0 2 FB1_14 27 I/O (b)
cnt<13> 3 0 0 2 FB1_15 28 I/O (b)
cnt<12> 3 0 0 2 FB1_16 35 I/O (b)
cnt<11> 3 0 0 2 FB1_17 30 GCK/I/O (b)
cnt<10> 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 12: cnt<15> 22: cnt<4>
2: clk_div1<0> 13: cnt<16> 23: cnt<5>
3: clk_div1<1> 14: cnt<17> 24: cnt<6>
4: clk_div1<2> 15: cnt<18> 25: cnt<7>
5: clk_div1<3> 16: cnt<19> 26: cnt<8>
6: cnt<0> 17: cnt<1> 27: cnt<9>
7: cnt<10> 18: cnt<20> 28: rst
8: cnt<11> 19: cnt<21> 29: state_FFd1
9: cnt<12> 20: cnt<2> 30: state_FFd2
10: cnt<13> 21: cnt<3> 31: state_FFd3
11: cnt<14>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
state_FFd3 XXXXXXXXXXXXXXXXXXXXXXXXXXXX..X......... 29
state_FFd2 XXXXXXXXXXXXXXXXXXXXXXXXXXXX.XX......... 30
state_FFd1 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX......... 31
cnt<9> XXXXXX..........X..XXXXXXXXX............ 16
cnt<8> XXXXXX..........X..XXXXXXX.X............ 15
cnt<7> XXXXXX..........X..XXXXXX..X............ 14
cnt<21> XXXXXXXXXXXXXXXXXXXXXXXXXXXX............ 28
cnt<20> XXXXXXXXXXXXXXXXXX.XXXXXXXXX............ 27
cnt<19> XXXXXXXXXXXXXXXXX..XXXXXXXXX............ 26
cnt<18> XXXXXXXXXXXXXXX.X..XXXXXXXXX............ 25
cnt<17> XXXXXXXXXXXXXX..X..XXXXXXXXX............ 24
cnt<16> XXXXXXXXXXXXX...X..XXXXXXXXX............ 23
cnt<15> XXXXXXXXXXXX....X..XXXXXXXXX............ 22
cnt<14> XXXXXXXXXXX.....X..XXXXXXXXX............ 21
cnt<13> XXXXXXXXXX......X..XXXXXXXXX............ 20
cnt<12> XXXXXXXXX.......X..XXXXXXXXX............ 19
cnt<11> XXXXXXXX........X..XXXXXXXXX............ 18
cnt<10> XXXXXXX.........X..XXXXXXXXX............ 17
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 29/25
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
clk_div2<7> 8 3<- 0 0 FB2_1 142 I/O (b)
(unused) 0 0 /\3 2 FB2_2 143 GSR/I/O (b)
clk_div1<0> 2 0 0 3 FB2_3 (b) (b)
cnt<6> 3 0 0 2 FB2_4 4 I/O (b)
cnt<5> 3 0 0 2 FB2_5 2 GTS/I/O (b)
cnt<4> 3 0 0 2 FB2_6 3 GTS/I/O (b)
cnt<3> 3 0 0 2 FB2_7 (b) (b)
cnt<2> 3 0 0 2 FB2_8 5 GTS/I/O (b)
cnt<1> 3 0 0 2 FB2_9 6 GTS/I/O (b)
cnt<0> 3 0 0 2 FB2_10 7 I/O (b)
clk_div2<12> 3 0 0 2 FB2_11 9 I/O (b)
clk_div1<2> 3 0 0 2 FB2_12 10 I/O (b)
clk_div1<3> 4 0 \/1 0 FB2_13 12 I/O (b)
clk_div1<1> 4 1<- \/2 0 FB2_14 11 I/O (b)
clk_div2<4> 7 2<- 0 0 FB2_15 13 I/O (b)
(unused) 0 0 \/5 0 FB2_16 14 I/O (b)
clk_div2<10> 7 5<- \/3 0 FB2_17 15 I/O (b)
clk_div2<9> 8 3<- 0 0 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 11: clk_div2<2> 21: cnt<2>
2: clk_div1<0> 12: clk_div2<3> 22: cnt<3>
3: clk_div1<1> 13: clk_div2<4> 23: cnt<4>
4: clk_div1<2> 14: clk_div2<5> 24: cnt<5>
5: clk_div1<3> 15: clk_div2<6> 25: cnt<6>
6: clk_div2<0> 16: clk_div2<7> 26: rst
7: clk_div2<10> 17: clk_div2<8> 27: state_FFd1
8: clk_div2<11> 18: clk_div2<9> 28: state_FFd2
9: clk_div2<12> 19: cnt<0> 29: state_FFd3
10: clk_div2<1> 20: cnt<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
clk_div2<7> XXXXXXXXXXXXXXXXXX.......XXXX........... 22
clk_div1<0> XX.......................X.............. 3
cnt<6> XXXXX.............XXXXXXXX.............. 13
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