buzzer.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   clk_div2<5>.CLK = clk;
    clk_div2<5>.EXP  =  !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>

MACROCELL | 6 | 13 | clk_div2<6>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 12 | 6 | 16
INPUTS | 20 | rst  | clk_div2<6>  | clk_div2<1>  | clk_div1<0>  | clk_div1<3>  | clk_div2<10>  | clk_div2<11>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | EXP18_.EXP  | clk
INPUTMC | 18 | 6 | 13 | 6 | 14 | 1 | 2 | 1 | 12 | 1 | 16 | 6 | 9 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 6 | 12
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 6 | 14
IMPORTS | 1 | 6 | 12
EQ | 53 | 
   clk_div2<6>.T = !rst & clk_div2<6>
;Imported pterms FB7_13
	# rst & clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div2<4> & clk_div2<5> & clk_div1<0> & 
	!clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & state_FFd2 & state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
;Imported pterms FB7_12
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   clk_div2<6>.CLK = clk;
    clk_div2<6>.EXP  =  !clk_div2<1> & !clk_div1<0>
	# !clk_div2<1> & !clk_div1<3>
	# clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & !state_FFd2 & state_FFd3

MACROCELL | 1 | 0 | clk_div2<7>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 16
INPUTS | 23 | rst  | clk_div2<7>  | clk_div2<0>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk_div2<10>  | clk_div2<11>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk  | EXP10_.EXP
INPUTMC | 21 | 1 | 0 | 6 | 11 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 1 | 16 | 6 | 9 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 1
INPUTP | 2 | 79 | 143
IMPORTS | 1 | 1 | 1
EQ | 35 | 
   clk_div2<7>.T = !rst & clk_div2<7>
	# rst & clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div2<4> & clk_div2<5> & clk_div2<6> & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
;Imported pterms FB2_2
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   clk_div2<7>.CLK = clk;

MACROCELL | 6 | 4 | clk_div2<8>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 16
INPUTS | 23 | rst  | clk_div2<8>  | clk_div2<0>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk_div2<10>  | clk_div2<11>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk  | EXP14_.EXP
INPUTMC | 21 | 6 | 4 | 6 | 11 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 1 | 16 | 6 | 9 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 6 | 5
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 6 | 3
IMPORTS | 1 | 6 | 5
EQ | 48 | 
   clk_div2<8>.T = !rst & clk_div2<8>
	# rst & clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div2<4> & clk_div2<5> & clk_div2<6> & 
	clk_div2<7> & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
;Imported pterms FB7_6
	# clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & !clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   clk_div2<8>.CLK = clk;
    clk_div2<8>.EXP  =  rst & !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>

MACROCELL | 1 | 17 | clk_div2<9>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 16
INPUTS | 23 | rst  | clk_div2<9>  | clk_div2<0>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk_div2<10>  | clk_div2<11>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk  | clk_div2<10>.EXP
INPUTMC | 21 | 1 | 17 | 6 | 11 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 1 | 16 | 6 | 9 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 16
INPUTP | 2 | 79 | 143
IMPORTS | 1 | 1 | 16
EQ | 37 | 
   clk_div2<9>.T = !rst & clk_div2<9>
	# rst & clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div2<4> & clk_div2<5> & clk_div2<6> & 
	clk_div2<7> & clk_div2<8> & clk_div1<0> & !clk_div1<1> & 
	!clk_div1<2> & clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
;Imported pterms FB2_17
	# clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & !clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   clk_div2<9>.CLK = clk;