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📄 buzzer.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
;Imported pterms FB7_8
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   clk_div2<11>.CLK = clk;
    clk_div2<11>.EXP  =  rst & !clk_div1<0>
	# !rst & !clk_div2<0>

MACROCELL | 6 | 14 | clk_div2<1>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 25 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 0 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 15
INPUTS | 23 | clk_div2<0>  | clk_div2<10>  | clk_div2<11>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk_div2<1>  | clk_div2<6>.EXP  | clk  | EXP19_.EXP
INPUTMC | 22 | 6 | 11 | 1 | 16 | 6 | 9 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 6 | 14 | 6 | 13 | 6 | 15
INPUTP | 1 | 143
IMPORTS | 2 | 6 | 13 | 6 | 15
EQ | 33 | 
   !clk_div2<1>.D = !clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	!clk_div2<2> & !clk_div2<3> & clk_div2<4> & clk_div2<5> & 
	!clk_div2<6> & !clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & state_FFd2 & state_FFd3
	# !clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	!clk_div2<2> & !clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & !state_FFd2 & state_FFd3
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<2> & clk_div2<3> & clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
;Imported pterms FB7_14
	# !clk_div2<1> & !clk_div1<0>
	# !clk_div2<1> & !clk_div1<3>
	# clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & !state_FFd2 & state_FFd3
;Imported pterms FB7_16
	# !rst
	# !clk_div2<0> & !clk_div2<1>
	# !clk_div2<1> & clk_div1<1>
	# !clk_div2<1> & clk_div1<2>
	# clk_div2<0> & clk_div2<1> & clk_div1<0> & 
	!clk_div1<1> & !clk_div1<2> & clk_div1<3>;
   clk_div2<1>.CLK = clk;

MACROCELL | 6 | 1 | clk_div2<2>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 0 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13
INPUTS | 23 | rst  | clk_div2<2>  | clk_div2<0>  | clk_div2<1>  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk_div2<10>  | clk_div2<11>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk  | out_OBUF.EXP
INPUTMC | 21 | 6 | 1 | 6 | 11 | 6 | 14 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 1 | 16 | 6 | 9 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 6 | 2
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 6 | 0
IMPORTS | 1 | 6 | 2
EQ | 18 | 
   clk_div2<2>.T = !rst & clk_div2<2>
	# rst & clk_div2<0> & clk_div2<1> & clk_div1<0> & 
	!clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & !state_FFd2 & state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
;Imported pterms FB7_3
	# clk_div2<10> & clk_div2<11> & clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>;
   clk_div2<2>.CLK = clk;
    clk_div2<2>.EXP  =  clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>

MACROCELL | 6 | 17 | clk_div2<3>
ATTRIBUTES | 8520480 | 0
OUTPUTMC | 25 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 0 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 16
INPUTS | 23 | clk_div2<0>  | clk_div2<10>  | clk_div2<11>  | clk_div2<1>  | clk_div2<2>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk_div2<3>  | EXP12_.EXP  | clk  | EXP20_.EXP
INPUTMC | 22 | 6 | 11 | 1 | 16 | 6 | 9 | 6 | 14 | 6 | 1 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 6 | 17 | 6 | 0 | 6 | 16
INPUTP | 1 | 143
IMPORTS | 2 | 6 | 0 | 6 | 16
EQ | 43 | 
   !clk_div2<3>.D = clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & !state_FFd2 & state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
;Imported pterms FB7_1
	# !rst
	# !clk_div2<0> & !clk_div2<3>
	# !clk_div2<1> & !clk_div2<3>
	# !clk_div2<2> & !clk_div2<3>
	# !clk_div2<3> & clk_div1<2>
;Imported pterms FB7_2
	# clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
;Imported pterms FB7_17
	# !clk_div2<3> & !clk_div1<0>
	# !clk_div2<3> & clk_div1<1>
	# !clk_div2<3> & !clk_div1<3>
	# clk_div2<10> & !clk_div2<11> & !clk_div2<3> & 
	clk_div2<4> & clk_div2<5> & clk_div2<6> & !clk_div2<7> & 
	clk_div2<8> & clk_div2<9> & !clk_div2<12> & state_FFd1 & 
	state_FFd2 & state_FFd3
	# !clk_div2<10> & clk_div2<11> & !clk_div2<3> & 
	clk_div2<4> & clk_div2<5> & clk_div2<6> & clk_div2<7> & 
	clk_div2<8> & !clk_div2<9> & !clk_div2<12> & state_FFd1 & 
	!state_FFd2 & !state_FFd3;
   clk_div2<3>.CLK = clk;

MACROCELL | 1 | 14 | clk_div2<4>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 16
INPUTS | 23 | rst  | clk_div2<4>  | clk_div2<0>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk_div2<10>  | clk_div2<11>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk  | clk_div1<1>.EXP
INPUTMC | 21 | 1 | 14 | 6 | 11 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 1 | 16 | 6 | 9 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13
INPUTP | 2 | 79 | 143
IMPORTS | 1 | 1 | 13
EQ | 28 | 
   clk_div2<4>.T = !rst & clk_div2<4>
	# rst & clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & state_FFd2 & state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
;Imported pterms FB2_14
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & !clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   clk_div2<4>.CLK = clk;

MACROCELL | 6 | 7 | clk_div2<5>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 16
INPUTS | 23 | rst  | clk_div2<5>  | clk_div2<0>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk_div2<10>  | clk_div2<11>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk  | EXP15_.EXP
INPUTMC | 21 | 6 | 7 | 6 | 11 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 1 | 16 | 6 | 9 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 6 | 6
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 6 | 8
IMPORTS | 1 | 6 | 6
EQ | 46 | 
   clk_div2<5>.T = !rst & clk_div2<5>
	# rst & clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div2<4> & clk_div1<0> & !clk_div1<1> & 
	!clk_div1<2> & clk_div1<3>
	# clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & state_FFd2 & state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
;Imported pterms FB7_7
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12> & state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & !clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 

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