buzzer.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

MDF Database:  version 1.0
MDF_INFO | buzzer | XC95144XL-10-TQ144
MACROCELL | 6 | 2 | out_OBUF
ATTRIBUTES | 4588322 | 0
OUTPUTMC | 2 | 6 | 2 | 6 | 1
INPUTS | 24 | rst  | out  | clk_div2<0>  | clk_div2<10>  | clk_div2<11>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk  | EXP13_.EXP
INPUTMC | 22 | 6 | 2 | 6 | 11 | 1 | 16 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 6 | 3
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 6 | 1
IMPORTS | 1 | 6 | 3
EQ | 57 | 
   out.T = !rst & out
	# rst & clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# rst & clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & !clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
;Imported pterms FB7_4
	# rst & clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# rst & clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# rst & clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# rst & !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# rst & !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
;Imported pterms FB7_5
	# rst & !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   out.CLK = clk;
    out_OBUF.EXP  =  clk_div2<10> & clk_div2<11> & clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & clk_div2<9> & 
	!clk_div2<12> & !state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>

MACROCELL | 6 | 11 | clk_div2<0>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 0 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 15
INPUTS | 22 | clk_div2<0>  | clk_div2<10>  | clk_div2<11>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | EXP17_.EXP  | clk
INPUTMC | 21 | 6 | 11 | 1 | 16 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 6 | 10
INPUTP | 1 | 143
EXPORTS | 1 | 6 | 12
IMPORTS | 1 | 6 | 10
EQ | 41 | 
   !clk_div2<0>.T = !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3
;Imported pterms FB7_11
	# rst & clk_div1<1>
	# rst & clk_div1<2>
	# rst & !clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	!state_FFd3
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3
;Imported pterms FB7_10
	# rst & !clk_div1<0>
	# !rst & !clk_div2<0>;
   clk_div2<0>.CLK = clk;
    clk_div2<0>.EXP  =  clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>

MACROCELL | 1 | 16 | clk_div2<10>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 16 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 15 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 16
INPUTS | 23 | rst  | clk_div2<10>  | clk_div2<0>  | clk_div2<11>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | state_FFd1  | state_FFd2  | state_FFd3  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk  | EXP11_.EXP
INPUTMC | 21 | 1 | 16 | 6 | 11 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 1 | 15
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 1 | 17
IMPORTS | 1 | 1 | 15
EQ | 49 | 
   clk_div2<10>.T = !rst & clk_div2<10>
;Imported pterms FB2_16
	# rst & clk_div2<0> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & clk_div2<4> & clk_div2<5> & clk_div2<6> & 
	clk_div2<7> & clk_div2<8> & clk_div2<9> & clk_div1<0> & 
	!clk_div1<1> & !clk_div1<2> & clk_div1<3>
	# clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;
   clk_div2<10>.CLK = clk;
    clk_div2<10>.EXP  =  clk_div2<0> & clk_div2<10> & !clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & !clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>

MACROCELL | 6 | 9 | clk_div2<11>
ATTRIBUTES | 4326176 | 0
OUTPUTMC | 24 | 6 | 2 | 6 | 11 | 1 | 15 | 6 | 9 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 12 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 10 | 1 | 1 | 1 | 13 | 1 | 16 | 6 | 3 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 10 | 6 | 13 | 6 | 16
INPUTS | 19 | rst  | clk_div2<11>  | clk_div2<0>  | clk_div2<10>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | EXP16_.EXP  | clk
INPUTMC | 17 | 6 | 9 | 6 | 11 | 1 | 16 | 6 | 14 | 6 | 1 | 6 | 17 | 1 | 14 | 6 | 7 | 6 | 13 | 1 | 0 | 6 | 4 | 1 | 17 | 1 | 2 | 1 | 13 | 1 | 11 | 1 | 12 | 6 | 8
INPUTP | 2 | 79 | 143
EXPORTS | 1 | 6 | 10
IMPORTS | 1 | 6 | 8
EQ | 46 | 
   clk_div2<11>.T = !rst & clk_div2<11>
	# rst & clk_div2<0> & clk_div2<10> & clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	clk_div1<0> & !clk_div1<1> & !clk_div1<2> & clk_div1<3>
;Imported pterms FB7_9
	# clk_div2<0> & clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & clk_div2<2> & clk_div2<3> & !clk_div2<4> & 
	!clk_div2<5> & clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & !state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & state_FFd1 & !state_FFd2 & 
	!state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & clk_div2<4> & 
	clk_div2<5> & !clk_div2<6> & !clk_div2<7> & clk_div2<8> & 
	clk_div2<9> & !clk_div2<12> & !state_FFd1 & state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	!clk_div2<1> & !clk_div2<2> & !clk_div2<3> & !clk_div2<4> & 
	clk_div2<5> & clk_div2<6> & clk_div2<7> & !clk_div2<8> & 
	!clk_div2<9> & !clk_div2<12> & state_FFd1 & !state_FFd2 & 
	state_FFd3 & clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
	# !clk_div2<0> & !clk_div2<10> & clk_div2<11> & 
	clk_div2<1> & !clk_div2<2> & clk_div2<3> & clk_div2<4> &