📄 mux.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: mux Date: 2-21-2006, 2:25PM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
9 /144 ( 6%) 30 /720 ( 4%) 21 /432 ( 5%) 0 /144 ( 0%) 16 /117 ( 14%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 0/18 0/54 0/90 0/15
FB2 0/18 0/54 0/90 0/15
FB3 0/18 0/54 0/90 0/15
FB4 2/18 7/54 4/90 2/15
FB5 0/18 0/54 0/90 0/14
FB6 6/18 7/54 22/90 6/13
FB7 0/18 0/54 0/90 0/15
FB8 1/18 7/54 4/90 1/15
----- ----- ----- -----
9/144 21/432 30/720 9/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 7 7 | I/O : 16 109
Output : 9 9 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 16 16
** Power Data **
There are 9 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 9 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
d<1> 4 7 FB4_1 118 I/O O STD FAST
en 0 0 FB4_11 132 I/O O STD FAST
d<7> 4 7 FB6_2 106 I/O O STD FAST
d<5> 2 7 FB6_4 111 I/O O STD FAST
d<4> 6 7 FB6_8 113 I/O O STD FAST
d<2> 6 7 FB6_9 116 I/O O STD FAST
d<3> 4 7 FB6_10 115 I/O O STD FAST
d<0> 0 0 FB6_11 119 I/O O STD FAST
d<6> 4 7 FB8_16 107 I/O O STD FAST
** 7 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
b<1> FB5_3 59 I/O I
c<1> FB5_7 66 I/O I
a FB5_8 56 I/O I
c<0> FB5_10 68 I/O I
b<2> FB5_11 58 I/O I
b<0> FB5_14 61 I/O I
c<2> FB5_15 64 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 23 I/O
(unused) 0 0 0 5 FB1_2 16 I/O
(unused) 0 0 0 5 FB1_3 17 I/O
(unused) 0 0 0 5 FB1_4 25 I/O
(unused) 0 0 0 5 FB1_5 19 I/O
(unused) 0 0 0 5 FB1_6 20 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 21 I/O
(unused) 0 0 0 5 FB1_9 22 I/O
(unused) 0 0 0 5 FB1_10 31 I/O
(unused) 0 0 0 5 FB1_11 24 I/O
(unused) 0 0 0 5 FB1_12 26 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 27 I/O
(unused) 0 0 0 5 FB1_15 28 I/O
(unused) 0 0 0 5 FB1_16 35 I/O
(unused) 0 0 0 5 FB1_17 30 GCK/I/O
(unused) 0 0 0 5 FB1_18 (b)
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 142 I/O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 0 5 FB2_13 12 I/O
(unused) 0 0 0 5 FB2_14 11 I/O
(unused) 0 0 0 5 FB2_15 13 I/O
(unused) 0 0 0 5 FB2_16 14 I/O
(unused) 0 0 0 5 FB2_17 15 I/O
(unused) 0 0 0 5 FB2_18 (b)
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 39 I/O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
(unused) 0 0 0 5 FB3_3 41 I/O
(unused) 0 0 0 5 FB3_4 44 I/O
(unused) 0 0 0 5 FB3_5 33 I/O
(unused) 0 0 0 5 FB3_6 34 I/O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
(unused) 0 0 0 5 FB3_9 40 I/O
(unused) 0 0 0 5 FB3_10 48 I/O
(unused) 0 0 0 5 FB3_11 43 I/O
(unused) 0 0 0 5 FB3_12 45 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 49 I/O
(unused) 0 0 0 5 FB3_15 50 I/O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 51 I/O
(unused) 0 0 0 5 FB3_18 (b)
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 7/47
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
d<1> 4 0 0 1 FB4_1 118 I/O O
(unused) 0 0 0 5 FB4_2 126 I/O
(unused) 0 0 0 5 FB4_3 133 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 128 I/O
(unused) 0 0 0 5 FB4_6 129 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 130 I/O
(unused) 0 0 0 5 FB4_9 131 I/O
(unused) 0 0 0 5 FB4_10 135 I/O
en 0 0 0 5 FB4_11 132 I/O O
(unused) 0 0 0 5 FB4_12 134 I/O
(unused) 0 0 0 5 FB4_13 137 I/O
(unused) 0 0 0 5 FB4_14 136 I/O
(unused) 0 0 0 5 FB4_15 138 I/O
(unused) 0 0 0 5 FB4_16 139 I/O
(unused) 0 0 0 5 FB4_17 140 I/O
(unused) 0 0 0 5 FB4_18 (b)
Signals Used by Logic in Function Block
1: a 4: b<2> 6: c<1>
2: b<0> 5: c<0> 7: c<2>
3: b<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
d<1> XXXXXXX................................. 7
en ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 52 I/O
(unused) 0 0 0 5 FB5_3 59 I/O I
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 53 I/O
(unused) 0 0 0 5 FB5_6 54 I/O
(unused) 0 0 0 5 FB5_7 66 I/O I
(unused) 0 0 0 5 FB5_8 56 I/O I
(unused) 0 0 0 5 FB5_9 57 I/O
(unused) 0 0 0 5 FB5_10 68 I/O I
(unused) 0 0 0 5 FB5_11 58 I/O I
(unused) 0 0 0 5 FB5_12 60 I/O
(unused) 0 0 0 5 FB5_13 70 I/O
(unused) 0 0 0 5 FB5_14 61 I/O I
(unused) 0 0 0 5 FB5_15 64 I/O I
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 69 I/O
(unused) 0 0 0 5 FB5_18 (b)
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 7/47
Number of signals used by logic mapping into function block: 7
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB6_1 (b)
d<7> 4 0 0 1 FB6_2 106 I/O O
(unused) 0 0 0 5 FB6_3 (b)
d<5> 2 0 0 3 FB6_4 111 I/O O
(unused) 0 0 0 5 FB6_5 110 I/O
(unused) 0 0 0 5 FB6_6 112 I/O
(unused) 0 0 \/1 4 FB6_7 (b) (b)
d<4> 6 1<- 0 0 FB6_8 113 I/O O
d<2> 6 1<- 0 0 FB6_9 116 I/O O
d<3> 4 0 /\1 0 FB6_10 115 I/O O
d<0> 0 0 0 5 FB6_11 119 I/O O
(unused) 0 0 0 5 FB6_12 120 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 121 I/O
(unused) 0 0 0 5 FB6_15 124 I/O
(unused) 0 0 0 5 FB6_16 117 I/O
(unused) 0 0 0 5 FB6_17 125 I/O
(unused) 0 0 0 5 FB6_18 (b)
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