state_machine.cmd_log

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

xst -intstyle ise -ifn __projnav/state_machine.xst -ofn state_machine.syr
ngdbuild -dd _ngo -uc state_machine.ucf -p xc9500 state_machine.ngc state_machine.ngd
cpldfit -p xc95108-15-PC84 -ofmt verilog -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 36 -pterms 25 -power std -localfbk -pinfbk state_machine.ngd
hprep6 -s IEEE1149 -n state_machine -i state_machine
taengine -f state_machine -w --format html1 -l e:\cindy\developboard\xc95108\state_machine/state_machine_html/tim/timing_report.htm
XSLTProcess "state_machine_build.xml"
xst -intstyle ise -ifn __projnav/state_machine.xst -ofn state_machine.syr
ngdbuild -dd _ngo -uc state_machine.ucf -p xc9500 state_machine.ngc state_machine.ngd
cpldfit -p xc95108-15-PC84 -ofmt verilog -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 36 -pterms 25 -power std -localfbk -pinfbk state_machine.ngd
hprep6 -s IEEE1149 -n state_machine -i state_machine
taengine -f state_machine -w --format html1 -l e:\cindy\developboard\xc95108\state_machine/state_machine_html/tim/timing_report.htm
XSLTProcess "state_machine_build.xml"
xst -intstyle ise -ifn __projnav/state_machine.xst -ofn state_machine.syr
ngdbuild -dd _ngo -uc state_machine.ucf -p xc9500xl state_machine.ngc state_machine.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt verilog -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper state_machine.ngd
hprep6 -s IEEE1149 -n state_machine -i state_machine
taengine -f state_machine -w --format html1 -l e:\temp\95144\veriloge\basic\state_machine/state_machine_html/tim/timing_report.htm
XSLTProcess "state_machine_build.xml"
xst -intstyle ise -ifn __projnav/state_machine.xst -ofn state_machine.syr
xst -intstyle ise -ifn __projnav/state_machine.xst -ofn state_machine.syr
ngdbuild -dd _ngo -uc state_machine.ucf -p xc9500xl state_machine.ngc state_machine.ngd
cpldfit -p xc95144xl-10-TQ144 -ofmt verilog -optimize speed -htmlrpt -loc on -slew fast -init low -inputs 54 -pterms 25 -unused float -power std -terminate keeper state_machine.ngd
hprep6 -s IEEE1149 -n state_machine -i state_machine
taengine -f state_machine -w --format html1 -l e:\temp\95144\veriloge\basic\state_machine/state_machine_html/tim/timing_report.htm
XSLTProcess "state_machine_build.xml"
xst -intstyle ise -ifn __projnav/state_machine.xst -ofn state_machine.syr
ngdbuild -intstyle ise -dd "e:\temp\spartan2\veriloge\basic\state_machine/_ngo" -nt timestamp -uc state_machine.ucf  -p xc2s50-TQ144-6 state_machine.ngc state_machine.ngd
map -intstyle ise -p xc2s50-TQ144-6 -cm area -pr b -k 4 -c 100 -tx off -o state_machine_map.ncd state_machine.ngd state_machine.pcf
par -w -intstyle ise -ol std -t 1 state_machine_map.ncd state_machine.ncd state_machine.pcf
trce -intstyle ise -e 3 -l 3 -s 6 -xml state_machine state_machine.ncd -o state_machine.twr state_machine.pcf
bitgen -intstyle ise -f state_machine.ut state_machine.ncd
ngdbuild -intstyle ise -dd "e:\temp\spartan2\veriloge\basic\state_machine/_ngo" -uc state_machine.ucf  -p xc2s50-tq144-6 state_machine.ngc state_machine.ngd
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o state_machine_map.ncd state_machine.ngd state_machine.pcf
par -w -intstyle ise -ol std -t 1 state_machine_map.ncd state_machine.ncd state_machine.pcf
trce -intstyle ise -e 3 -l 3 -s 6 -xml state_machine state_machine.ncd -o state_machine.twr state_machine.pcf
bitgen -intstyle ise -f state_machine.ut state_machine.ncd