state_machine.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: state_machine.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "state_machine.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "state_machine"
Output Format                      : NGC
Target Device                      : xc2s50-6-TQ144

---- Source Options
Top Module Name                    : state_machine
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : state_machine.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "state_machine.v"
Module <state_machine> compiled
No errors in compilation
Analysis of file <"state_machine.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <state_machine>.
	state0 = <u>000
	state1 = <u>001
	state2 = <u>010
	state3 = <u>011
	state4 = <u>100
	state5 = <u>101
	state6 = <u>110
	state7 = <u>111
Module <state_machine> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <state_machine>.
    Related source file is "state_machine.v".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state> of Case statement line 60 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'init' attribute on signal <state> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 8                                              |
    | Inputs             | 0                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0000 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 24-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
Unit <state_machine> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:3]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 011
 100   | 100
 101   | 101
 110   | 110
 111   | 111
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Counters                         : 1
 24-bit up counter                 : 1
# Registers                        : 3
 1-bit register                    : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <state_machine> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block state_machine, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : state_machine.ngr
Top Level Output File Name         : state_machine
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 18

Macro Statistics :
# Registers                        : 1
#      24-bit register             : 1
# Adders/Subtractors               : 1
#      24-bit adder                : 1

Cell Usage :
# BELS                             : 91
#      GND                         : 1
#      INV                         : 3
#      LUT1                        : 9
#      LUT1_L                      : 14
#      LUT2                        : 1
#      LUT3                        : 8
#      LUT3_L                      : 1
#      LUT4                        : 7
#      MUXCY                       : 23
#      VCC                         : 1
#      XORCY                       : 23
# FlipFlops/Latches                : 27
#      FDC                         : 24
#      FDCE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 17
#      IBUF                        : 1
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      23  out of    768     2%  
 Number of Slice Flip Flops:            27  out of   1536     1%  
 Number of 4 input LUTs:                40  out of   1536     2%  
 Number of bonded IOBs:                 18  out of     96    18%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 27    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 7.291ns (Maximum Frequency: 137.155MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 9.317ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 7.291ns (frequency: 137.155MHz)
  Total number of paths / destination ports: 378 / 30
-------------------------------------------------------------------------
Delay:               7.291ns (Levels of Logic = 3)
  Source:            cnt_14 (FF)
  Destination:       state_FFd1 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_14 to state_FFd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   1.085   1.206  cnt_14 (cnt_14)
     LUT4:I0->O            1   0.549   1.035  _n000054 (CHOICE60)
     LUT3_L:I0->LO         1   0.549   0.100  _n0000523 (N31)
     LUT4:I0->O            3   0.549   1.332  _n0000135 (_n0000)
     FDCE:CE                   0.886          state_FFd2
    ----------------------------------------
    Total                      7.291ns (3.618ns logic, 3.673ns route)
                                       (49.6% logic, 50.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 21 / 7
-------------------------------------------------------------------------
Offset:              9.317ns (Levels of Logic = 2)
  Source:            state_FFd3 (FF)
  Destination:       c<7> (PAD)
  Source Clock:      clk rising

  Data Path: state_FFd3 to c<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            10   1.085   1.980  state_FFd3 (state_FFd3)
     LUT3:I2->O            1   0.549   1.035  state_Out61 (c_1_OBUF)
     OBUF:I->O                 4.668          c_1_OBUF (c<1>)
    ----------------------------------------
    Total                      9.317ns (6.302ns logic, 3.015ns route)
                                       (67.6% logic, 32.4% route)

=========================================================================
CPU : 4.54 / 5.02 s | Elapsed : 5.00 / 5.00 s
 
--> 

Total memory usage is 74756 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)